2011－24V BCD Process ESD（LDMOS）－MD Ker

semico_ljj

Improving Safe Operating Area of LDMOS Array
With Embedded Silicon Controlled
Rectifier for ESD Protection
in a 24-V BCD Process

Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 9, SEPTEMBER 2011

Abstract—In high-voltage technologies, silicon-controlled rectifier
(SCR) is usually embedded in output arrays to provide a
robust and self-protected capability against electrostatic discharge
(ESD). Although the embedded SCR has been proven as an excellent
approach to increasing ESD robustness, mistriggering of
the embedded SCR during normal circuit operating conditions
can bring other application reliability concerns. In particular,
the safe operating area (SOA) of output arrays due to SCR insertion
has been seldom evaluated. In this paper, the impact of
embedding SCR to the electrical SOA (eSOA) of an n-channel
LDMOS (nLDMOS) array has been investigated in a 24-V bipolar
CMOS–DMOS process. Experimental results showed that the
nLDMOS array suffers substantial degradation on eSOA due to
embedded SCR. Design approaches, including a new proposed
poly-bending (PB) layout, were proposed and verified in this paper
to widen the eSOA of the nLDMOS array with embedded SCR.
Both the high ESD robustness and the improved SOA of circuit
operation can be achieved by the new proposed PB layout in the
nLDMOS array.

Index Terms—Electrostatic discharge (ESD), poly-bending (PB)
layout, reliability, safe operating area (SOA), silicon-controlled
rectifier (SCR).

semico_ljj

best。。。

floatice

have a look!

mtwumtwu

good reference for ESD design of BCD process

duduxy

KER怎么又发了这么多paper

texascowboy

thank you

pingdandan

好好，谢谢分享

JJmeow

感謝您的分享

envi

感謝分享

cliassh

let me have a look