Vref is the resultant of the a positive tempco voltage (multiple delta_Vt's) and a negative tempco voltage (Vbe). Each process/device has its own device characteristic therefore the sweet zero tempco spot is slightly different from process to process, although they all fall within the 1.25v range.
BTW, bandgap circuit has no relation with silicon bandgap. It just happens to be so in the 1.25 voltage range. You can scale it down to any voltage if you chose current summation instead of voltage summation.
if you design opamp based bandgap ckt(which is that there
is one opamp ckt in the ptat ckt(propotional to absolute temperature ckt)
then you must care about the dc offset voltage(input systematic offset voltage
and input random device mismatch voltage)of the opamp you used
because the bandgap voltage
accuracy will be strongly affected by the dc offset voltage of the opamp(see Razavi's
analog ckt design text book Fig 11.12 (bandgap ckt chapter)
if you increase opamp open loop dc gain then it will decrease
input systematic offset voltage;if you choose very large device size for input
differential pair for the opamp and layout style is common centroid
then it will decrease input random device mismatch voltage