【推荐】2011.9.9xilinx FPGA免费培训资料（7系列 planahead 嵌入式）

pontiff

给那些没有机会去现场的兄弟们
PDF格式为培训课件，压缩包为上机实验内容。一楼为7系列

pontiff

二楼为PlanAhead,Xilinx今后主推的IDE

pontiff

三楼为嵌入式总线AXI with Microblaze

seth0001

恩，不错，学习下

digital_bird

这个很新哦

pontiff

自己顶一下。

thales_cui

zhen bu cuo. 3x

hongshao

好东西 啊 楼主真是好人啊

nirvanauscn

三楼还有实验4-6吗，不介意打包上传替弟兄们省点钱吧。多谢了，正在做这方面的东西。
Lab Descriptions
The MicroBlaze processor labs are based on the AXI interconnect.
▪ Lab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.
▪ Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the FPGA and download the application.
▪ Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.
▪ Lab 4: Building Custom AXI IP for an Embedded System – Create and add a custom AXI peripheral (LCD interface) to your design by using the Create or Import Peripheral Wizard.
▪ Lab 5: BFM Simulation – Use the ISim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.
▪ Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in an ISE design project.

adefan

Thanks.