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发表于 2011-8-16 22:18:38
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回复 1# 陈涛
1) clock is propagated -> CTS done
2) large fan out at U7/Y, HFN buffer/create buffer tree
n12 long net leads to large cap, reroute or insert buffer on route
capture clock delay 1ns shorter then launch, optimize clock tree to delay the capture reg
large lib setup time, need to check .lib. |
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