美资上市公司RFIC layout

Sunnyjiao

Job Description   有兴趣的联系我sunny@genhr.com   MSN :stsh1020@hotmail.com   13641777463/021-60481748You will work closely with a world-class team of IC designers to perform physical design of highly-integrated, high-performance ICs with RF, analog, mixed-signal, and digital signal processing systems integrated on a single chip.  Responsibilities include physical design of demanding mixed-signal and RF layout blocks, chip-level floorplanning, place and route of digital blocks, top-level chip assembly, full-chip verification, chip tapeout, and mask data verification.  This position will require strong communication and problem-solving skills.  Versatility, initiative and the ability to adapt to a dynamic startup environment are essential.


Requirement:
•        BS Degree in EE (with relevant specialization) or higher, with 5+ years of industrial working experience.
•        Experience in analog and digital IC physical design with exposure to top-level assembly and chip tapeout procedures
•        Solid understanding of physical, electrical rules and DFM rules for fine-geometry CMOS processes
•        Direct experience in RF layout and knowledge of semiconductor devices and fabrication principles
•        Proficiency in block level floorplanning, understanding of device matching issues such as WPE and STI
•        Ability to estimate and minimize parasitics prior to detailed layout extraction
•        Comprehension of isolation issues and ability to create effective shielding / isolation structures
•        Experience with industry-standard layout and verification tools (Cadence: Viruoso, Assura, Encounter; Mentor: Calibre) and proficiency in a Unix workstation environment
•        Experience with PCB layout tools, lab test and measurement equipment, VBA programming or LabView programming beneficial.