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本帖最后由 suk.qi 于 2011-7-20 15:48 编辑
主要是stanford大学的培训课程，包含了Cu制程的各个要点。
Gate_Dielectric (EOT ~ 20% TOX, Id∝Q_V, Oxide degrading Mechanism).pdf
Gate_Dielectric (SiO2 - SiON in NH3_N2O_NO, high~K).pdf
IBM_Silicides_Mann.pdf
Interconnection Silicides (same as polycides - salicides and metal gate).pdf
Interconnections -Copper & Low K Dielectrics (low RC delay, good EM, T↓t↑Gsize↑rho↓u↑).pdf
Interconnections -Copper & Low K Dielectrics.pdf
Low Power CMOS Process Technology (SS-leak, SiON, μ-Strained Liner, Hybrid Orientation, Wf, BTB, Halo, MG, SOI, FinFET, k~2.4, Tcap).pdf
Polycides, Salicides & Metal gate (segregation, diffusion and consumption).pdf
Scaling trends for the on-chip power modeling (Interconnection, Logic, Memory, Leakage and clock).pdf
Trends (α-scaling, Nanoscale, High-k, DG-FinFET, Isolation, Backend 3-D).pdf
TSUPREM4_Slides.pdf
USING TSUPREM-IV IN SWEET HALL.pdf
Integrated circuit isolation technologies.pdf
Future Devices (Heterostructure_DG MOSFET_Center Channel DG-FET, HEMT, I-MOS) - 3.pdf
Future Devices (Organic FETs,Molecular FET, Schottky SD Nanotube FETs) - 2.pdf
Future Devices (UTPDSOI, Non Planar MOSFETs, GeMOS - u3900, Egmin -Ileak_high) - 1.pdf
Interconnect Al (Mechanical properties, EM minimized@GB, Air-Gap).pdf
Interconnect Low k (weak polarization - nonpolar low-dielectric, minimize the moisture, Porous Materials).pdf
Interconnect Scaling (Multilayer, HF - Skin Effect, Delay, Resistivity, Thermal, Low-k).pdf
Shallow Junctions Slides (OED_ORD_TED, I↑V↓,defect ED in POLY several times faster, PAI, Bandgap Engineering, cl0_d0).pdf
Report of Lab activities (NMOS processing & simulation).pdf
GateOxNO_Kwong.pdf
GateOx_Schuegraf.pdf
NitOx_Kwong.pdf
04Apr23 Stanford Process.part2.rar
(13.83 MB, 下载次数: 411 )
04Apr23 Stanford Process.part1.rar
(13.83 MB, 下载次数: 404 )
04Apr23 Stanford Process.part3.rar
(13.83 MB, 下载次数: 427 )
04Apr23 Stanford Process.part4.rar
(12.65 MB, 下载次数: 337 )
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2011-7-20 15:30:59
