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芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
楼主: indianhill

[招聘更新]美资Agere(朗讯)上海高薪招聘存储和通讯方向IC设计师

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发表于 2006-11-21 17:34:00 | 显示全部楼层


原帖由 jingli888ca 于 2006-11-7 14:55 发表


对呀,上50万,你再看看,肯定人山人海。。。

但凡,能领着十来二十个人,开发个一年半两年的项目的牛人,整天忙得恨不得生出四只手来,那会到这里来灌水?

你们公司,不错,但不是最好的。项目都是 ...





jingli888ca 好像什么都知道, 佩服!
发表于 2006-11-25 18:25:41 | 显示全部楼层
艾,世态炎凉啊。
发表于 2006-11-27 21:14:44 | 显示全部楼层
刚半年经验~~~
慢慢培养中
 楼主| 发表于 2006-12-1 17:33:20 | 显示全部楼层
看来大家对Agere上海研发中心目前的状况不太了解,目前招聘的职位,很多都是目前通讯和存储方面最前沿的技术领域。

10月28日,44职位;
11月1日,41职位;
12月1日,37个职位虚位以待。

[ 本帖最后由 indianhill 于 2006-12-2 15:33 编辑 ]
发表于 2006-12-6 16:38:30 | 显示全部楼层

LSI逻辑并购agere 前景如何

 楼主| 发表于 2006-12-13 10:12:52 | 显示全部楼层
感谢大家关注LSI Logic和杰尔的合并。

可以看一下下面这篇文章,我觉得还是比较正面和中肯的 。

解读LSI Logic和杰尔大合并:消费和通信的技术融合
http://www.esmchina.com/ART_8800072838_617671_3e28b8e2200612_no.HTM

Agere目前仍然按照以前的既定计划正常运行,合并对于我们上海的招聘不会有任何的影响,而且,由于合并后的新公司已经成为存储芯片领域里的业界领袖,网络和消费芯片部门也得到了加强,LSI--Agere在中国仍然会坚持扩大研发团队, 一定会加大对于中国地区研发的投入。
 楼主| 发表于 2006-12-14 10:11:19 | 显示全部楼层

更新职位信息(Digital):

更新职位信息(Digital):

[ 本帖最后由 indianhill 于 2007-1-19 17:48 编辑 ]
 楼主| 发表于 2006-12-14 10:12:16 | 显示全部楼层

更新职位信息(Analog):

Analog IC Designer for Hard Disk Drive Read Channel – STO000000GV   (存储部门)
  Position Description:

A read channel analog IC design engineer’s duties include working within a highly motivated product development team to create and modify high speed mixed signal integrated circuits. You will support the cross functional team in taking our concepts thru to high volume production and assist us in becoming the market leaders in this Mass Storage (hard disk drive) industry.


Job Responsibilities:

l         Design the next generation Analog circuits for the Read Channel macro.
l         Work with Architecture and Digital Development Teams to achieve optimal implementation.
l         Verify and validate the functionality of the analog circuits.


Qualifications
Job Qualifications:

l         Communicate effectively within a global business environment (must be proficient in both spoken and written English)
l         3+ years experience in chip level CMOS analog design
l         Experience with high speed opamps, continuous time filters, wide band A/D & D/A converters, and PLLs preferred
l         Must have experience with Cadence tools.
l         Experience in developing simulation and verification test benches
l         Excellent technical troubleshooting and demonstrated problem solving skills
l         Must be willing to follow a structured design approach including design for reuse and provide thorough design documentation
l         

Education/Certifications:
Required Degree: BS
Preferred Degree: MS or PhD
Preferred Major: Microelectronics, Electrical Engineering or related discipline


Analog IC Design Engineer (Mid-Level, 4-6 Years Exp.) – STO000000FN
(存储部门)
  

Job Responsibilities


Duties will include working within a Product Development Team to create (design, layout, and evaluate) new circuit architectures, and to modify existing circuit architectures, verify functionality of designs, prepare and present Design Reviews to internal groups and external customers, write technical reports, attend technical conferences in the areas of data storage and advanced IC design. Specific responsibilities include:



-          Communicate effectively within a global business environment (must be proficient in both spoken and written English).

-          Perform transistor level, analog and mixed signal integrated circuit design of various cells and blocks within custom chips for the hard disk drive industry. Examples of some blocks are: voltage regulators, bandgap circuits, data converters (DAC, ADS), low noise amplifiers, line drivers, multipliers, temperature sensing circuits, filters, operational amplifiers, variable gain amplifiers,  control logic, serial port controller.

-          Support the integration of all cells and blocks into a completed integrated circuit

-          Work directly with customers to determine the system requirements, write specifications, and guide them on the use of our preamplifier products.

-          Conduct detailed design reviews of cell and block level circuits.

-          Perform design validation thru simulation with Cadence software.

-          Use highspeed electronic characterization equipment to evaluate and debug the functionality of the silicon

-          Perform transistor level and block level layout (physical design).

-          Provide technical support and guidance to a cross functional team of engineers thru all phases of product development which includes: test, yield, characterization, reliability analysis, qualification, and release to manufacturing.

-          Adhering to schedule, die size, and power commitments.





Qualifications
Functional/Industry Knowledge
Required:
- Minimum of 4-6 years Analog IC Design experience in a product development environment
- Proven Analog IC Design skills
- Proven experimental skills and lab/bench expertise
- Strong written and verbal communication skills



Desired:
- Past experience in a lead position giving guidance to other engineers

Education/Certifications
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline


                  
Pysical Design Engineer – STO000000H1   (存储部门)  


Position Description:

Join our new design team in Shanghai by working on leading edge Mass Storage silicon solutions . Strong individual needed to support product line growth. The candidate will work on leading edge solutions in ASIC, full custom and SoC environment. The ideal candidate will have demonstrated experience/exposure to custom high-speed analog physical design from initial design phase through to manufacturing. Excellent communication skills are needed, as existing teams span multiple locations.



Qualifications
Job Qualifications:

Expertise in full custom analog layout, signal integrity, power and electro-migration analysis, design rule and connectivity verification is required. Familiarity with digital physical design, basic circuit designs, manufacturing and IC packaging desirable.

q     Must be technically adept

q     strong team player

q     ability to manage multiple priorities and schedules

q     must have strong communication skills.

q     Minimum education is a two year technical degree, BSEE preferred.

q     A minimum of 5 years experience in Physical Analog Design is required.
 楼主| 发表于 2006-12-14 10:13:27 | 显示全部楼层
44职位空缺10月28日
41职位空缺11月6日
40 职位空缺11月10日
37 职位空缺11月24日
38 职位空缺12月14日 (增加了几个Senior 职位)


更多的招聘职位请参看:

http://www.agere.com/careers/careersearch.html

选择“China", 看今天还有多少空缺职位。

欢迎有兴趣的朋友投递中、英文简历至:agerechina@gmail.com
发表于 2006-12-16 10:51:47 | 显示全部楼层
要工作经验要求啊...
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