[招聘更新]美资Agere（朗讯）上海高薪招聘存储和通讯方向IC设计师

indianhill

[招聘]Agere（朗讯）上海高薪诚聘高级IC设计师(29职位01/19) 请版主置顶

Agere system （杰尔系统） 的前身是朗讯科技半导体部门，目前在上海徐家汇甲级写字楼设有分公司和研发中心。Agere Systems 在通讯半导体，手机基带芯片和硬盘控制器芯片等方面处于世界最前沿，大家平时经常接触的三星、夏新手机、希捷和迈拓的硬盘，中兴、华为的基站等产品当中，核心芯片都来自Agere。


上海研发中心现诚聘通讯和存储方面的IC designer，要求一年以上工作经验，部分职位要求3-5+年经验。美国独资企业，薪水颇具竞争力。应届毕业的本科和研究生暂时不招收，敬请谅解。

具体的职位信息请参看：
http://www.agere.com/careers/careersearch.html   

选择 “China", search.

有意者请发送中、英文简历至：agerechina@gmail.com

如有任何疑问或问题，也可发送：agerechina@gmail.com

谢谢。

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部分热招职位：

        
Analog IC Design Engineer (Mid-Level, 4-6 Years Exp.) – TEN0000002H--   通讯
  

Job Description
   
Duties will include working within a Product Development Team to create (design, layout, and evaluate) new circuit architectures, and to modify existing circuit architectures, verify functionality of designs, prepare and present Design Reviews to internal groups and external customers, write technical reports, attend technical conferences in the areas of data storage and advanced IC design.



Qualifications
Functional/Industry Knowledge
Required:
- Minimum of 4 - 6 years Analog IC Design experience in a product development environment
- Perform transistor level, analog and mixed signal integrated circuit design of various cells and blocks
- Proven Analog IC Design skills
- Proven experimental skills and lab/bench expertise
- Strong written and verbal communication skills in both Mandarin and English
  
Education/Certifications

Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline


ASIC Verification Engineer (Junior-Level, 1-3 Years Exp.) – TEN00000022--通讯

  

Job Description

Duties will include working within a Product Development Team to develop reusable block-level and ASIC testbenches using HVL. Develop new ASIC verification environments to support ASIC development. Maintain existing ASIC verification environments. Review RTL architectural and implementation specifications. Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced multiprotocol networking ASICs. Define and develop application tests required to verify ASICs meet functional and performance goals. Define and implement functional coverage plans. Define and implement code coverage plans. Develop testing and regression methodologies for new verification flow. Coordinate test plan implementation and regressions with remote team. Incorporate reusability into all aspects of the verification environment. Develop/maintain/enhance environment tools/scripts/makefiles.



Qualifications
Functional/Industry Knowledge
Required:

- Minimum of 1-3 years ASIC Verification experience in a product development environment
- Proven ASIC Design Verification skills
- Fluent in Verilog for design verification
- Experience with SpecMan
- Experience with one or more scripting languages: awk, Perl, python
- Experience with C/C++
- Superior debugging skills for large ASIC designs

- Knowledge of data and telecommunication networking(TDM/IP/ATM/Ethernet)
- Strong written and verbal communication skills in both Chineses and English
- Adaptable to evolving customer requirements


Desired:
- Past experience in a lead position giving guidance to other engineers

- Profound knoledge of DS3/E3

Education/Certifications
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline

Digital IC Design Engineer (Mid-Level, 4-6 Years Exp.) – TEN0000004 --通讯

Duties will include working within a Product Development Team to perform (design, layout, and evaluate) architectural definition, digital logic design, and verification. Candidate will be involved in upfront product planning activities including architectural tradeoffs, die size estimation, packaging selection, and technology assessment. As a member of a design team, candidate will be responsible for managing the design from concept to product launch.



Qualifications
Functional/Industry Knowledge
Required:
- Minimum of 4-6 years Digital IC Design experience in a product development environment
- Proven Digital IC Design skills
- Must be familiar with RTL coding, synthesis, static timing analysis, simulation, audits, timing closure,  CAD tools, and design support
- Must be willing to follow a structured design approach including design for reuse and provide thorough design documentation

- Strong written and verbal English communication skills

- PCI-Express prefer

Education/Certifications
Required Degree: MS
Preferred Major: Electrical Engineering or related discipline

Physical Design Engineer - Place & Route (Mid-Level, 4-6 Years Exp.) – TEN0000004J  通讯

  

Duties will include working within a Product Development Team to work on leading edge ASIC
solutions in full custom and SoC environments. Design IC devices in conformance with both
Agere Systems and customer requirements and sound design principles; Place and rount(layout)
of integrated circuites to meet design requirements; Prepare project evaluations in confirmance
with compnay policies/procedures; Provide CAD assistance to customer engineers and new staff
as required and/or requested; Keep up-to-date with all technical memos; Attend peer reviews
and provide feedback to ensure success of peer designs. Ideal candidate will have
experience/exposure to ASIC and full custom high-speed digital flows from design handoff
through manufacturing. Excellent communication skills are needed, as the existing team spans

multiple locations.



Qualifications
Functional/Industry Knowledge

Required:
- Minimum of 2-5 years experience in Physical Design in a product development environment
- Proven physical design experience
- Expertise in circuit design, place and routing, signal integrity, power analysis, CTS design, DFT,
design rule and connectivity verification
- Good analytical and debugging skills
- Extremely disciplined in conducting checks and audits
- Must be technically adept, a strong team player, ability to manage multiple priorities
- Strong written and verbal communication skills
- Ability to interact intelligently and politely with customers



Desired:
- Familiarity with analog physical design, manufacturing and IC packaging
- Past experience in a lead position giving guidance to other engineers



Education/Certifications
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline

Pysical Design Engineer [5+years]– STO000000GZ  --存储

  

Job Description

Join our new design team in Shanghai by working on leading edge Mass Storage silicon solutions . Strong individual needed to support product line growth. The candidate will work on leading edge solutions in ASIC, full custom and SoC environment. The ideal candidate will have demonstrated experience/exposure to custom high-speed analog physical design from initial design phase through to manufacturing. Excellent communication skills are needed, as existing teams span multiple locations.



Qualifications
Job Qualifications:

Expertise in full custom analog layout, signal integrity, power and electro-migration analysis, design rule and connectivity verification is required. Familiarity with digital physical design, basic circuit designs, manufacturing and IC packaging desirable.

q     Must be technically adept

q     strong team player

q     ability to manage multiple priorities and schedules

q     must have strong communication skills.

q     Minimum education is a two year technical degree, BSEE preferred.

q     A minimum of 5 years experience in Physical Analog Design is required.


System Application Engineer for Sonet/SDH Mapper, TDM, Packet Integrated Circuits [3+ Years]– TEN0000002L -- 通讯 Job Responsibilities:

This is a Systems Applications Engineering position that involves the support of applications for our customers on Sonet/SDH, TDM, and TDM to ATM and Packet converter products. Support includes providing technical help on Agere products designed into customer systems, reviewing customer schematics, and configuring the devices.


Qualifications
Functional/Industry Knowledge:


Required:
-  Minimum of 3 years Engineering experience in telecom product development. Experience with Sonet/SDH, TDM, ATM, and Packet systems.
-  Familiar with network architectures and applications
-  Experience in hardware development or debugging
-  Excellent problem solving skills
-  Fluent spoken and written English
-  Experience with writing documents (data-sheet, application-notes, etc.)


Desired
-  customer support experience
-  knowledge of interface,e.g. PCI bus, Motorola local bus, UTOPIA, POSPHY.
-  Knowledge and experience in LINUX and VxWorks RTOS



Education/Certifications
Preferred Degree: MS
Preferred Major: MSCE or MSEE



SAE Manager [8+Years]– TEN0000000I  通讯
  

Job Description
   SAE Manager will be responsible to lead a world class SAE team to successful feature development, reference design, system solution proposal, customer issue support on System, Software, Hardware within APAC region, and global in the future.
SAE Manager will work with all levels of management including BU, Marketing, Sales, FAE, customers to effectively assign SAE resource, provide project control, support and schedule management, make sure of good execution, keep all moving forward as committed.



Qualifications
Functional/Industry Knowledge
Required:
Candidates must have had success in personally managing complex, schedule critical design projects. Requires excellent team leadership skills, communication, flexibility, responsiveness and demonstrated success managing large cross-functional initiatives.
-  8+ years combined design & project management experience in a data networking or telecom product development.
-  Strong facilitation and meeting management skills
-  Able to work and coordinate with multiple teams on resource assignment, schedule setup and progress track.
-  Able to lead a team in the development of work breakdown structures and schedules
-  Able to analyze schedules to understand problem areas, bottlenecks, and areas for improvement
-  Experience in embedded software development with C code, familiar with development based on VxWorks, Linux.
-  Experience in Hardware development on schematics, PCB, high speed design, familiar with PowerPC, ARM, DDR/DDRII/FCRAM/SSRAM, Utopia, SPI, PCI, GE/FE etc.
-  Familiar with network architectures and applications, traffic management and resource management algorithms and functions
-  Experience or deep understanding of wireline (ATM, TCP/IP, MPLS, ML/MC-PPP, Gigabit/Fast Ethernet, PDH, SONET) and wireless (NodeB, RNC) networking protocols.
-  Excellent problem solving and communication skills.
-  Experience in customer support for ATM, IP/Ethernet and Transportation products.



Desired:
-  software/hardware experience in Agere's Network Processor.



Education/Certifications
Required Degree: MS
Preferred Degree: MS/Ph.D

Preferred Major: Electronical Engineering or Computer Science

[ 本帖最后由 indianhill 于 2007-1-19 17:54 编辑 ]

srouyang

要经验阿，钱多不？

djgirl

应届不要，要别人培养好的？

azoth

好像钱不少

indianhill

奇怪，为什么收到的简历这么少呢？

看来大家对Agere不太了解，Agere在很多领域都是开拓者和市场强者，Agere脱胎于贝尔实验室和朗讯科技，是晶体管、激光器件、蓝牙、WiFI, DSP等很多技术的发明人，执有IC行业~7000项专利。在朗讯的时代，Agere几乎就是通讯半导体的代名词。大家所熟知的Samsung 手机，中兴华为的基站、Seagate硬盘，Maxtor硬盘，Ipod等产品里面，Agere都扮演重要角色。

settleinsh

上面写的都是要几年的经验，真正有那么多经验的人是不会到处找工作的
总是有猎头去挖

老扁

年薪能到50万不，如果有可以给你推荐几个，：）

一粒尘埃

kanle ,kan bu dong

iceman

符合经验要求的应该也不多吧

jingli888ca

原帖由 老扁 于 2006-11-6 12:12 发表
年薪能到50万不，如果有可以给你推荐几个，：）

对呀，上50万，你再看看，肯定人山人海。。。

但凡，能领着十来二十个人，开发个一年半两年的项目的牛人，整天忙得恨不得生出四只手来，那会到这里来灌水？

你们公司，不错，但不是最好的。项目都是五年前北美的东西，主要是搞仿真验证，没有全流程的开发，所以，吸引到的以学习练手的居多。03~05年间，没有调过一次薪水，气氛有些沉闷，流失了一两个Leader，有人说它是motoroloa的经停站。。。

[ 本帖最后由 jingli888ca 于 2006-11-7 15:30 编辑 ]