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[size=120%]Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios (Analog Circuits and Signal Processing)
By Emanuele Lopelli, Johan van der Tang, Arthur van Roermund
- Publisher: Springer
- Number Of Pages: 235
- Publication Date: 2010-12-24
- ISBN-10 / ASIN: 9400701829
- ISBN-13 / EAN: 9789400701823
Wireless sensor networks have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. Unfortunately, radio power consumption is still a major bottleneck to the wide adoption of this technology. Different directions have been explored to minimize the radio consumption, but the major drawback of the proposed solutions is a reduced wireless link robustness.
The primary goal of Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios is to discuss, in detail, existing and new architectural and circuit level solutions for ultra-low power, robust, uni-directional and bi-directional radio links.
Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios guides the reader through the many system, circuit and technology trade-offs he will be facing in the design of communication systems for wireless sensor networks. Finally, this book, through different examples realized in both advanced CMOS and bipolar technologies opens a new path in the radio design, showing how radio link robustness can be guaranteed by techniques that were previously exclusively used in radio systems for middle or high end applications like Bluetooth and military communications while still minimizing the overall system power consumption.
Table of ContentsContents
Acronyms
Introduction
- Application Field
- System Requirements
- Energy Scavenging Techniques
- Super-capacitor Size Estimation
- Battery Size Estimation
- General Wireless Node Requirements
- Link Robustness
- Data Rate
- Range and Sensitivity
- Turn-on and Synchronization Time
- Technology Comparison and Trade-offs
- State of the Art
- Research in Industries
- Research in Universities
- The Objectives of This Book
- Outline of the Book
System-Level and Architectural Trade-offs
- Modulation Schemes for Ultra-low Power Wireless Nodes
- Impulse Radio Transceivers
- Back-scattering for RFID Applications
- Sub-sampling
- Super-regenerative
- Spread-Spectrum Systems
- Direct Sequence Spread-Spectrum
- Frequency Hopping Spread Spectrum
- DSSS Versus FHSS
- Modulation Formats
- Optimal Data-Rate
- Constant Duty-Cycle
- Constant Time Between Two Consecutive Transmissions
- Transmitter Architectures
- Direct Conversion
- Two-Step Conversion
- Offset PLL
- Receiver Architectures
- Zero-IF
- Super-heterodyne
- Low-IF
- Conclusions
FHSS Systems: State-of-the-Art and Power Trade-offs
- Synchronization
- Stepped Serial Search
- Matched Filter Acquisition
- Two-Level Acquisition
- Acquisition Methods Comparison
- State-of-the-Art FHSS Systems
- FH Synthesizer Architectures
- Specifications for Ultra-low-power Frequency-Hopping Synthesizers
- PLL Power Estimation Model
- VCO
- Loop Filter
- Charge Pump
- PFD and Frequency Divider
- Complete PLL Power Model
- DDFS Power Estimation Model
- DDFS Specifications for Frequency-Hopping Synthesizers
- AA-filter Power Consumption
- Phase Accumulator and ROM Power Consumption Estimation
- DAC Power Consumption Estimation
- R-2R DAC
- Charge Redistribution DAC
- Power Dissipation of the Whole DDFS
- Summarizing Discussion
- Conclusions
A One-Way Link Transceiver Design
- General Guidelines for Transmitter Design
- Transmitter Architecture
- Concepts and Block Diagrams
- Frequency Planning and Pre-distortion
- Deterministic Errors
- Stochastic Errors
- Transmitter Specifications
- Transmitted Power
- Synthesizer Phase Noise
- Synthesizer Coarse and Fine Tuning Ranges
- Oscillator-Divider Based Architecture
- Oscillator Design
- Frequency Divider Design
- Output Buffer
- Power-VCO Based Architecture
- Power-VCO Design Procedure
- Receiver Architecture
- RX-TX Center Frequency Alignment Algorithm
- Residual Frequency Error after Pre-distortion
- Temperature or Supply Variations
- Finite Precision of the Pre-distortion Algorithm
- Implementation and Experimental Results
- TX Node Implementation
- DSP
- RF Front-End
- Interface Between the DSP and the RF Front-End
- Antenna
- IC Board for PVT Measurements
- RG Implementation
- Measurement Results
- Benchmarking
- Conclusions
A Two-Way Link Transceiver Design
- Transmitter Design General Guidelines
- Transmitter Architecture
- Synthesizer Design
- Baseband Frequency Hopping Synthesizer Specifications
- Baseband Frequency-Hopping Synthesizer Architecture
- Harmonic Rejection Based Frequency Synthesizer
- Concluding Remarks
- Baseband Frequency Hopping Synthesizer Implementation
- Mixer Design
- Programmable Dividers
- Walsh Function Based Harmonic Rejection Block
- LP-notch Filter
- Generation of a 288-MHz Reference Clock
- Receiver Design at System Level
- Receiver Link Budget Analysis
- Propagation Link Budget Analysis
- Link Budget Analysis of Discrete Parts
- Link Budget Analysis for Integrated Parts
- Inter-modulation Distortion and Receiver Linearity
- Receiver Building Blocks State-of-the-Art
- Active Mixer
- Anti-aliasing Baseband Filter
- Analog-to-Digital Converters
- Simulation and Experimental Results
- Baseband Synthesizer Without the LP-notch Filter
- Stand Alone Tunable LP-notch Filter
- Complete Frequency Hopping Baseband Synthesizer
- Benchmarking
- Conclusions
Summary and Conclusions
Appendix Walsh Based Harmonic Rejection Sensitivity Analysis
References
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发表于 2011-6-21 07:55:36
