Challenges in the design high-speed clock and data recovery circuits

drjiachen · 发表于 2011-6-10 10:40:45

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Behzad Razavi, University of California, Los Angeles

ABSTRACT
This article describes the challenges in the
design of monolithic clock and data recovery circuits
used in high-speed transceivers. Following
an overview of general issues, the task of phase
detection for random data is addressed. Next,
Hogge, Alexander, and half-rate phase detectors
are introduced and their trade-offs outlined.
Finally, a number of clock and data recovery
architectures are presented.

Challenges in the design high-speed clock and data recovery circuits.pdf (104.39 KB, 下载次数: 168 )

piao · 发表于 2011-6-16 23:59:37

thanks for sharing

widlarfan · 发表于 2011-6-17 07:40:14

Thanks for sharing!

yudgern · 发表于 2011-8-14 13:33:23

好文章

liumm · 发表于 2012-2-3 18:05:05

Thanks for sharing!

david90542 · 发表于 2012-4-30 14:12:22

Thanks for sharing!

wxp29082 · 发表于 2012-6-29 21:11:42

Thanks for sharing!

JJmeow · 发表于 2013-6-15 17:46:31

感謝分享

zhujun134 · 发表于 2015-8-15 11:36:14

thanks

fwutsairlin · 发表于 2016-4-30 12:02:14

thanks!

[资料] Challenges in the design high-speed clock and data recovery circuits

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