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本帖最后由 kaku817kaku817 于 2011-5-28 20:01 编辑
Application Notes
The Application_Notes collection contains the following application notes: - AN119 - 'AHB masters and slaves' design for Virtex 2 Logic Tile.
- AN123 - Logic Tile 'IT1 GPIO example' design.
- AN125 - Adding additional processors to the PB926EJ-S using Core Tiles.
- AN128 - Logic Tile 'Flashing LED' design.
- AN136 - Using Core Tiles stand-alone.
- AN146 - Using EB with example AHB Logic Tile.
- AN148 - Using EB with CT7TDMI, CT926EJ-S, and CT1136JF-S Core Tiles.
- AN151 - Using EB with example AXI Logic Tile.
- AN152 - Using EB with CT11MPCore Core Tile.
- AN158 - Using EB with CT1156T2F-S Core Tile.
- AN170 - 'AHB masters and slaves' design for Virtex 4 and Virtex 5 Logic Tiles.
- AN177 - Using EB with CT1176JZF-S Core Tile.
- AN217 - Using EB with CT-R4F Core Tile.
AN119
Application note AN119 is an example design to implement AHB masters and slaves in a Logic Tile based system. The design allows interfacing to the Logic Tile SSRAM, LEDs, switches and clocks. The push switch is used to generate a master transfer into the PB926EJ-S baseboard.
The following board combinations are supported: - Core Module + Integrator/IM-LT1 + LT-XC2V6000
- Core Module + Integrator/IM-LT1 + LT-XC2V8000
- Integrator/CP + Core Module + Integrator/IM-LT1 + LT-XC2V6000
- Integrator/CP + Core Module + Integrator/IM-LT1 + LT-XC2V8000
- PB926EJ-S + LT-XC2V6000
- PB926EJ-S + LT-XC2V8000
Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
AN123
Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board.
The following board combinations are supported: - Core Module + Integrator/IM-LT1 + LT-XC2V6000 + IT1
- Core Module + Integrator/IM-LT1 + LT-XC2V8000 + IT1
- Integrator/CP + Core Module + Integrator/IM-LT1 + LT-XC2V6000 + IT1
- Integrator/CP + Core Module + Integrator/IM-LT1 + LT-XC2V8000 + IT1
- PB926EJ-S + LT-XC2V6000 + IT1
- PB926EJ-S + LT-XC2V8000 + IT1
Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
AN125
This example design enables you to use an arm7TDMI, ARM926EJ-S, or ARM1136JF-S Core Tile on a PB926EJ-S. A Logic Tile is also required.
The following board combinations are supported: - PB926EJ-S + {LT-XC2V6000 + CT7TDMI}
- PB926EJ-S + {LT-XC2V8000 + CT7TDMI}
- PB926EJ-S + {LT-XC2V6000 + CT926EJ-S}
- PB926EJ-S + {LT-XC2V8000 + CT926EJ-S}
- PB926EJ-S + {LT-XC2V6000 + CT1136JF-S}
- PB926EJ-S + {LT-XC2V8000 + CT1136JF-S}
AN128
Application note AN128 is a simple 'flashing LED' example design to demonstrate the process of creating FPGA images and programming them into Logic Tiles.
The following board combinations are supported:
Logic Tiles - LT-XC2V6000
- LT-XC2V8000
- LT-XC4VLX160
- LT-XC4VLX200
- LT-XC5VLX330
running on top of baseboards - IM-LT1
- EB + CT7TDMI
- EB + CT926EJ-S
- EB + CT1136JF-S
- EB + CT1156T2F-S
- EB + CT1176JZF-S
- EB + CT11MPCore
- PB1176JZF-S
- PB11MPCore
- PBA8
AN136
This example design shows how to use Core Tiles as individual units powered through an IM-LT1. A Logic Tile is also required.
The following board combinations are supported: - Integrator/IM-LT1 + {LT-XC2V6000 + CTxxx} + ...
- Integrator/IM-LT1 + {LT-XC2V8000 + CTxxx} + ...
- Integrator/IM-LT1 + {LT-XC2V6000 + CT926EJ-S} + {IT1} + ...
- Integrator/IM-LT1 + {LT-XC2V8000 + CT926EJ-S} + {IT1} + ...
AN146
This example shows how to use the EB baseboard with an example AHB Logic Tile.
The following board combinations are supported:
Logic Tiles - LT-XC2V6000
- LT-XC2V8000
- LT-XC4VLX160
- LT-XC4VLX200
- LT-XC5VLX330
running on top of baseboards - EB + CT7TDMI
- EB + CT926EJ-S
- EB + CT1136JF-S
AN148
This example shows how to use the EB baseboard with CT7TDMI, CT926EJ-S, or CT1136JF-S Core Tiles.
The following board combinations are supported: - EB + CT7TDMI
- EB + CT926EJ-S
- EB + CT1136JF-S
AN151
This example shows how to use the EB baseboard with an example AXI Logic Tile.
The following board combinations are supported:
Logic Tiles - LT-XC2V6000
- LT-XC2V8000
- LT-XC4VLX160
- LT-XC4VLX200
- LT-XC5VLX330
running on top of baseboards - EB + CT1156T2F-S
- EB + CT1176JZF-S
- EB + CT11MPCore
- EB + CT-R4F
- PB1176JZF-S
- PB11MPCore
- PB-A8
- PBX-A9
AN152
This example shows how to use the EB baseboard with a CT11MPCore Core Tile.
The following board combination is supported:
AN158
This example shows how to use the EB baseboard with a CT1156T2F-S Core Tile.
The following board combination is supported:
AN170
This example shows how to implement AHB Peripherals in Logic Tiles.
The following board combinations are supported: - PB926EJ-S + LT-XC4VLX160
- PB926EJ-S + LT-XC4VLX200
- PB926EJ-S + LT-XC5VLX330
AN177
This example shows how to use the EB baseboard with a CT1176JZF-S Core Tile.
The following board combination is supported:
AN217
This example shows how to use the EB baseboard with a CT-R4F Core Tile.
The following board combination is supported:
AN119.zip
(4.35 MB, 下载次数: 2476 )
AN123.zip
(4.27 MB, 下载次数: 2113 )
AN125.zip
(8.78 MB, 下载次数: 2275 )
AN128.part1.rar
(14.31 MB, 下载次数: 877 )
AN128.part2.rar
(14.31 MB, 下载次数: 516 )
AN128.part3.rar
(6.07 MB, 下载次数: 2106 )
AN136.zip
(5.2 MB, 下载次数: 2121 )
AN146.zip
(4.64 MB, 下载次数: 2451 )
AN148.part1.rar
(14.31 MB, 下载次数: 524 )
AN148.part2.rar
(12.7 MB, 下载次数: 717 )
AN151.zip
(13.24 MB, 下载次数: 852 )
AN152.zip
(13.71 MB, 下载次数: 463 )
AN158.part1.rar
(14.31 MB, 下载次数: 648 )
AN158.part2.rar
(608.62 KB, 下载次数: 304 )
AN170.zip
(5.32 MB, 下载次数: 2223 )
AN177.part1.rar
(14.31 MB, 下载次数: 472 )
AN177.part2.rar
(1004.39 KB, 下载次数: 297 )
AN217.part1.rar
(14.31 MB, 下载次数: 562 )
AN217.part2.rar
(1.56 MB, 下载次数: 392 )
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发表于 2011-5-27 00:09:30
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