Low Power, Wide Range ADPLL for Video Applications

zhou__jian · 发表于 2014-12-20 16:23:30

谢谢大家

zhou__jian · 发表于 2014-12-20 16:24:11

找了很久了

walterVSI · 发表于 2015-10-21 13:40:15

谢谢分享

cdting · 发表于 2016-6-21 10:34:29

非常感謝～～～～

fwutsairlin · 发表于 2016-7-12 16:31:12

THANK YOU

Ryggeor · 发表于 2017-5-2 21:28:16

thnx!

amigo.change · 发表于 2017-5-2 22:21:05

cdting · 发表于 2017-5-3 05:18:20

非常感謝~~~~

sp065441 · 发表于 2017-6-20 15:15:48

This thesis presented a low power all digital phase locked loop (ADPLL) for the video
applications. The ADPLL has wide range of operating input frequency from 10 kHz to 150 kHz.
The output range of ADPLL is from 10 MHz to 300 MHz can be used for a variety of
applications. The circuit of ADPLL is implemented in a CMOS 65-nm technology using a
supply voltage of 1 V.

smrecnik · 发表于 2017-6-21 10:08:54

thanks for sharing

[资料] Low Power, Wide Range ADPLL for Video Applications

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