Low Power, Wide Range ADPLL for Video Applications

kevinwjs

Implementation of Low Power, Wide Range ADPLL for Video Applications.pdf (1.14 MB, 下载次数: 591 )

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Table of Contents
1  Background and Introduction  ............................................................................................................... 1
1.1  Introduction .................................................................................................................................. 1
1.2  Video AFE  ...................................................................................................................................... 1
1.3  Digitizing Channel ......................................................................................................................... 1
1.3.1  Input Multiplexer and DC Clamp  ........................................................................................... 2
1.3.2  Programmable Gain Amplifier .............................................................................................. 2
1.3.3  Input Low Pass Filter  ............................................................................................................. 2
1.3.4  Analog to Digital Converter  ................................................................................................... 3
1.4  Time/Reference Channel .............................................................................................................. 4
1.4.1  Phase Locked Loop  ................................................................................................................ 4
1.4.2  Delay Locked Loop ................................................................................................................ 5
1.5  Reference  ...................................................................................................................................... 6
2  Analog Front End (AFE) ......................................................................................................................... 7
2.1  Introduction .................................................................................................................................. 7
2.2  Simplified Video AFE Block Diagram  ............................................................................................. 7
2.3  Video Data Concept [1]  ................................................................................................................. 8
2.4  Video Image .................................................................................................................................. 9
2.4.1  Interlaced and Non-Interlaced  ............................................................................................ 10
2.5  Video Resolution  ......................................................................................................................... 12
2.5.1  Standard Definition Video  ................................................................................................... 12
2.5.2  Enhanced Definition Video ................................................................................................. 13
2.5.3  High Definition Video  .......................................................................................................... 13
2.6  Color Spaces  ................................................................................................................................ 13
2.6.1  RGB Color Space  .................................................................................................................. 13
2.6.2  YUV Color Space  .................................................................................................................. 15
2.6.3  YIQ Color Space  ................................................................................................................... 15
2.6.4  YCbCr Color Space  ............................................................................................................... 15
2.7  References .................................................................................................................................. 18
3  Phase Locked Loop  .............................................................................................................................. 19
3.1  Applications of PLL  ...................................................................................................................... 20 vi
3.1.1  Recovery of Clock  ................................................................................................................ 20
3.1.2  Deskewing  ........................................................................................................................... 20
3.1.3  Clock Distribution  ................................................................................................................ 20
3.1.4  Frequency Synthesis ........................................................................................................... 21
3.1.5  Reduction of Noise and Jitter  .............................................................................................. 22
3.1.6  Generations of Clock  ........................................................................................................... 23
3.1.7  To Reduce Interference....................................................................................................... 23
3.2  Basic PLL Principle [11]  ................................................................................................................ 23
3.3  PLL Architecture  .......................................................................................................................... 24
3.4  Analog PLLs ................................................................................................................................. 24
3.4.1  Phase Detector [2] .............................................................................................................. 25
3.4.2  Charge Pump [2] ................................................................................................................. 28
3.4.3  Shortcomings of Charge Pump [7]  ...................................................................................... 29
3.4.4  Loop Filter [8]  ...................................................................................................................... 30
3.4.5  Loop Filter Design Issues  ..................................................................................................... 30
3.4.6  Charge Pump with Phase Frequency Detector ................................................................... 31
3.4.7  Voltage Controlled Oscillator (VCO)  .................................................................................... 33
3.4.8  Performance Parameters of VCOs [2]  ................................................................................. 34
3.4.9  Divider  ................................................................................................................................. 36
3.4.10  Varieties of Dividers  ............................................................................................................ 36
3.5  Digital PLLs and All-Digital PLLs [5] ............................................................................................. 37
3.6  Basic Architecture of ADPLL  ........................................................................................................ 38
3.7  Different Approaches  .................................................................................................................. 38
3.8  Why Digital PLL............................................................................................................................ 41
3.9  References .................................................................................................................................. 42
4  Behavioral Model  ................................................................................................................................ 43
4.1  Architecture Selection................................................................................................................. 43
4.2  Behavioral Model of Selected Architecture  ................................................................................ 46
4.3  References .................................................................................................................................. 51
5  Schematic Level Description of the ADPLL and Simulation Results  .................................................... 52
5.1  Circuit Components .................................................................................................................... 52
5.2  Phase and Frequency Detector (PFD) ......................................................................................... 52 vii
5.2.1  D-Flip Flop ........................................................................................................................... 52
5.2.2  Schematic of Phase Frequency Detector (PFD)................................................................... 56
5.3  Time-to-Digital Converter (TDC) [3]  ............................................................................................ 58
5.4  Digital Loop Filter (DLPF)  ............................................................................................................. 60
5.4.1  Multiplier  ............................................................................................................................. 62
5.5  Digital Controlled Oscillator (DCO) ............................................................................................. 64
5.5.1  DCO Delay Cell A ................................................................................................................. 65
5.5.2  DCO Delay Cell B ................................................................................................................. 67
5.6  Stability Analysis ......................................................................................................................... 68
5.7  Simulation Results  ....................................................................................................................... 70
5.7.1  For hsync = 15.625 kHz ....................................................................................................... 70
5.7.2  For hsync = 67.5 kHz ........................................................................................................... 71
5.7.3  For hsync = 107.184 kHz ..................................................................................................... 71
5.8  References .................................................................................................................................. 75
6  Conclusion and Future works.............................................................................................................. 76
6.1  Circuit optimization  ..................................................................................................................... 76
6.2  Single DCO  ................................................................................................................................... 76
6.3  Noise Analysis ............................................................................................................................. 76
6.4  Layout  ..........

tm1986

开刷传哦

chlliu

很好，谢谢！

rockycheng

Thank you very much!

panghui

谢谢分享！

fhchen2002

回复 1# kevinwjs


    谢谢分享！

mscyc0909

- Page#: 95
- Year: 2010
- Coclusion:
This thesis presented a low power all digital phase locked loop (ADPLL) for the video
applications. The ADPLL has wide range of operating input frequency from 10 kHz to 150 kHz.
The output range of ADPLL is from 10 MHz to 300 MHz can be used for a variety of
applications. The circuit of ADPLL is implemented in a CMOS 65-nm technology using a
supply voltage of 1 V.

loveyahoo

好资料，正好用上，谢谢

cyydx

好东西，多谢分享

zhengyongzheng

Low Power, Wide Range ADPLL for Video Applications