|
|
发表于 2011-9-1 21:46:55
|
显示全部楼层
TSMC user confirms Magma Titan takes mins vs. weeks for 2nd design
As part of TSMC's internal evaluation of key design
tools provided by various EDA suppliers, we had the opportunity to use the
Magma's TAM first-hand. We have actually used it twice, with good results.
The first time we optimized a small op-amp for a first-order sigma-delta
ADC in TSMC N40LP CMOS process. The ADC clocked at 100 MHz and runs off a
1.1 V power (0.95 V worst-case). It uses core 40 nm CMOS transistors.
TAM allowed us to meet speed and open-loop gain specs in the most power-
efficient way possible, across process corners.
We used 3 to 5 corners for the initial analysis, and 17 worst-case process
corners for the final run. We have verified the final design using corner
and Monte-Carlo analysis in Cadence Spectre, and now also in silicon. The
circuit behaves as expected. (Actually we believe that it is more robust
than what our designers could have made it by hand.)
More recently, we used Titan for a higher level of optimization.
Our team developed a scalable architecture for a high-performance (95 dB+)
Audio ADC. It's currently in a 0.18 um CMOS process but can easily be
retargeted to any other similar process. This ADC is based on a second
-order, multi-bit sigma-delta architecture. Topology involves two op-amps,
which have to be sized and optimized very carefully in order to meet the
speed, settling and noise requirements. The op-amps drive two sets of
switched capacitors, which are optimized in conjunction with the op-amps.
We were able to code all the relevant circuit equations into Titan. We ran
it to synthesize the whole design hierarchically. We supply a top-level
spec (the SNR of the ADC). TAM then optimizes the circuit all the way down
to the size of every transistor and capacitor, so that total power
consumption (and area) are minimized. Again, the optimized design has been
verified using circuit simulations. No silicon results are available yet |
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
