Base_EDI 10.10.000_lnx86

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Encounter Digital Implementation System                                                                                                                                                                                                                                                                                                                                                        
Physical implementation for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes
Encounter Digital Implementation System is an integrated solution that provides the fastest deterministic path to silicon realization. By leveraging and preserving design intent, enabling higher levels of abstraction, and ensuring quick convergence, it optimizes the implementation of giga-gate–scale, low-power, mixed-signal, and advanced node designs. In a single environment, Encounter Digital Implementation System supports RTL synthesis, rapid design exploration, accurate chip feasibility analysis, full-chip virtual prototyping, full-chip digital implementation, and in-design signoff. With an early, precise view of design feasibility, engineers can progress immediately to full-scale implementation and final signoff for large-scale, complex designs—without ever leaving the solution environment.

Predictability and convergence

• Combines the power of RTL synthesis, early design exploration, full-chip prototyping and design implementation, in-design DFM, and final signoff analysis in a single environment
• Enables design exploration and accurate chip feasibility analysis, including automated floorplan synthesis and ranking
• Supports location-based on-chip-variation technologies and the latest methodologies for statistical timing and leakage analysis and optimization

Productivity and faster time to market

• Supports hierarchical methodologies, including bottom-up block-based flows, top-down black-box flows, and hybrid flows with partitioning and time budgeting
• Provides a new post-assembly closure flow that enables more transparent hierarchical abstraction during top-level assembly and optimization
• Performs fast and accurate optimization and analysis in the flat physical implementation flow by leveraging the new single-step advanced engine for SI and timing analysis
• Delivers signoff-driven implementation and intuitive, visual features for global timing, power, and clock debug and diagnostics

Scalability in performance

• Delivers industry-leading performance and capacity for large, complex chips
• Offers a complete, end-to-end, multi-core parallel processing backplane and infrastructure

Product differentiation with lower costs

• Provides a tapeout-proven solution for complex design closure and low-power, mixed-signal, advanced node design implementation and optimization
• Supports comprehensive multi-mode/multi-corner analysis and optimization in all steps across the design flow
• Enables concurrent chip/package design and optimization with integrated capabilities such as automatic area and peripheral I/O placement and optimization, and flip-chip RDL routing
• Allows floorplanning, implementation, and analysis of 3D stacked-die designs to optimize heterogeneous processes/dies
• Ensures fewer iterations and faster convergence with in-design 3D-IC signoff extraction and analysis of timing, power, and thermal characteristics across multiple dies

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