IEEE-Standard-754 compliant double-precision floating point unit

eagleice

The following describes the IEEE-Standard-754 compliant, double-precision floating point unit,
written in Verilog.  The module consists of the following files:

1.
fpu_double.v (top level)
2.
fpu_add.v
3.
fpu_sub.v
4.
fpu_mul.v
5.
fpu_div.v
6.
fpu_round.v
7.
fpu_exceptions.v


And a testbench file is included, containing 50 test-case operations:
1.
fpu_tb.v

This unit has been extensively simulated, covering all operations, rounding modes, exceptions
like underflow and overflow, and even the obscure corner cases, like when overflowing from
denormalized to normalized, and vice-versa.  

The floating point unit supports denormalized numbers,
4 operations (add, subtract, multiply, divide), and 4 rounding
modes (nearest, zero, + inf, - inf).  The unit was synthesized with an
estimated frequency of 230 MHz, for a Virtex5 target device.  The synthesis results
are below.  fpu_double.v is the top-level module, and it contains the input
and output signals from the unit.  The unit was designed to be synchronous with
one global clock, and all of the registers can be reset with an synchronous global reset.
When the inputs signals (a and b operands, fpu operation code, rounding mode code) are
available, set the enable input high, then set it low after 2 clock cycles.  When the
operation is complete and the output is available, the ready signal will go high.  To start
the next operation, set the enable input high.

Each operation takes the following amount of clock cycles to complete:
1.
addition :
20 clock cycles
2.
subtraction:
21 clock cycles
3.
multiplication:
24 clock cycles
4.
division:
71 clock cycles

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