Continuous-Time Filter FOURTH ORDER EQUIRIPPLE Automatic Tuning

hi_china59

A CMOS 500 MHZ CONTINUOUS-TIME FOURTH ORDER 0.05° EQUIRIPPLE
LINEAR PHASE FILTER WITH AUTOMATIC TUNING

A Thesis
by
PANKAJ PANDEY
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
May 2003



ABSTRACT
A CMOS 500 MHz Continuous-Time Fourth Order 0.05° Equiripple
Linear Phase Filter with Automatic Tuning. (May 2003)
Pankaj Pandey, B.E., Regional Engineering College, Surat, India
Chair of Advisory Committee: Dr. Jose Silva-Martinez
The growing demand of portable electronic equipment and system-on-a-chip has
been pushing the industry to design circuits with very low power supply voltage and low
power consumption. The Hard Disk drive industry is looking for developments in the
read channel chip to push the data rates to higher speed, along with a low voltage and low
cost solution. Read channel requires high-speed linear phase filters to meet these
objectives. The primary objective of this project is to design, layout, and characterize a
4th-order continuous-time equiripple linear phase filter with automatic tuning system. The
main requirements for design are high speed, low group delay variations, good linearity
and power efficiency.
This filter features wide cut-off frequency 500MHz, which is far beyond the
current state-of-the-art. The linear phase filter is based on Gm-C biquadratics. Higher
speed has been achieved by minimizing the parasitics and a complementary input stage
OTA. A common mode feedback (CMFB), which ensures stability at such high
frequencies, has also been designed. The inaccuracies of the filter are compensated by
using a simple automatic tuning system.
The design is fabricated in 0.35 m TSMC CMOS process technology. The design
was simulated in Cadence using SPICE models provided by MOSIS for the 0.35 m TSMC
process in the presence of parasitic capacitance and transistor non- idealities. Cut-off
frequency of 500 MHz was achieved along with a 9% variation in the group delay.
iv
To my parents and sister
v
ACKNOWLEDGMENTS
I would like to express gratitude to my advisor Dr. Jose Silva-Martinez, for his
constant guidance, support and patience throughout this research work. I am deeply
indebted to him for all the knowledge and help he has extended to me. I would also like
to thank my committee members for their valuable suggestions and their cooperation.
I am indebted to my colleagues in the AMSC group who have helped me to
enhance my knowledge through various discussions and interactions. Special mention
goes to Ming Deng Chen, Husseyin Dinc and Narayan Prasad Ramachandran. Finally I
am grateful to my parents and sister who inspired me to pursue my dreams.
vi
TABLE OF CONTENTS
CHAPTER Page
I INTRODUCTION............................................................................................. 1
A. Architecture of Hard Disk Drive ................................................................... 2
1. Previous Work ........................................................................................ 4
B. Organization of the Thesis ............................................................................ 5
II LINEAR PHASE FILTERS.............................................................................. 7
A. Group Delay Response .................................................................................. 7
B. Transfer Function of the Filter ...................................................................... 9
C. Building Blocks of the Filter ......................................................................... 11
1. Two Integrator Loop .............................................................................. 11
2. Lossy Integrator ..................................................................................... 13
3. Realization of a Biquad ......................................................................... 14
4. Fully Differential Implementation......................................................... 17
III DESIGN OF SUITABLE OTA......................................................................... 19
A. Design Considerations for High Frequency Applications ............................. 19
1. Effect of Parasitic Capacitor.................................................................. 19
2. Effect of Saturation Voltage (VDSAT) on the OTA................................. 20
3. Effect of Non-dominant Poles ............................................................... 21
4. Possible OTA Implementations ............................................................. 21
B. OTA Architecture.......................................................................................... 25
1. Linearization Techniques....................................................................... 26
2. Effective gm of the OTA employed........................................................ 27
C. Design Specifications and Considerations for the OTA ............................... 29
1. Minimum Requirements from the OTA ................................................ 29
vii
CHAPTER Page
2. Small Signal Model of the OTA............................................................ 31
D. Simulation Results of the OTA ..................................................................... 35
IV DESIGN OF COMMON-MODE FEEDBACK CIRCUIT .............................. 40
A. Design Considerations for Common-Mode Feedback Circuit ...................... 40
1. Why Common-Mode control is Needed ................................................ 40
2. Sensing and Amplification Circuit ........................................................ 41
B. Possible Implementation of CMFB Circuit................................................... 43
1. A Simple CMFB Circuit ........................................................................ 44
2. A Current Feedback Based CMFB ........................................................ 46
C. Design Considerations for the New Common-Mode Scheme ...................... 48
D. Simulation Results......................................................................................... 50
V DESIGN OF TUNING CIRCUIT..................................................................... 55
A. Overview of Tuning Circuit .......................................................................... 55
1. Why Tuning Circuit is Required ............................................................ 55
2. General Concepts in Tuning................................................................... 55
B. Possible Tuning Implementations ................................................................. 57
1. Prominently Used Tuning Techniques ................................................... 57
C. Implementation of a Tuning Scheme ............................................................ 59
1. Operation of the Tuning Circuit ............................................................ 61
2. Tuning Circuit Specifications and Design ............................................. 63
D. Simulations Results of the Tuning Circuit .................................................... 67
1. Tuning Voltage ...................................................................................... 67
2. Filter Output with the Tuning Voltage .................................................. 68
3. Variation of the Tuning Voltage with Load Capacitor .......................... 69
4. Rectified Voltage ................................................................................... 70
viii
CHAPTER Page
VI SIMULATION RESULTS OF THE FILTER.................................................. 73
A. Schematic Level Simulation Results of Biquads Without Tuning................ 73
1. Estimation of the Parasitic Capacitance ................................................ 73
2. Schematic Level Simulation Results of Biquad1 .................................. 75
3. Schematic Level Simulation Results of Biquad2 .................................. 78
B. Schematic Level Simulation Results of Overall Filter Without Tuning ....... 82
C. Schematic Level Simulation Results of Overall Filter With Tuning ............ 93
D. Post Layout Simulation Results of the Overall Filter Without Tuning......... 97
E. Post Layout Simulation Results of the Filter With Tuning........................... 105
VII SUMMARY AND CONCLUSIONS................................................................ 111
REFERENCES.............................................................................................................. 112
VITA ............................................................................................................................. 116

apteye

thanks

skygardon

不错的资料，感谢分享！

xmujaylight

非常感谢楼主分享

semico_ljj

精彩。。。

semico_ljj

keyi...

Beidou

看看哈！

wushangkeji

不错的资料，感谢分享

efong

THANK YOU

quhuaibo

good material