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本帖最后由 sunmingming512 于 2011-4-15 18:35 编辑
不解释，直接源码
36位加法分频器 duty 1:35
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder36 is
port (clk,rst,en : in std_logic;
cq : out std_logic_vector(5 downto 0);
cout : out std_logic );
end adder36;
architecture sun of adder36 is
begin
process (clk,rst,en)
variable cqi :std_logic_vector (5 downto 0);
begin
if rst = '1' then cqi:=(others =>'0');
elsif clk'event and clk='1' then
if en='1' then
if cqi<35 then cqi:=cqi+1;
else cqi:= (others =>'0');
end if;
end if;
end if; -- if cqi>="100011" then cout<=not cout;
if cqi=35 then cout <='1';
else cout <='0';
end if;
cq<=cqi;
end process;
end sun;
三八译码器 高电平输出
library ieee;
use ieee.std_logic_1164.all;
entity ymq38 is
port (din : in std_logic_vector (2 downto 0);
dout ： out std_logic_vector (7 downto 0) );
end;
architecture behav of ymq38 is
begin
process (din)
begin
if (din="001") then dout <="00000001";
elsif (din="010") then dout <="00000010";
elsif (din="011") then dout <="00000100";
elsif (din="100") then dout <="00001000";
elsif (din="101") then dout <="00010000";
elsif (din="110") then dout <="00100000";
elsif (din="111") then dout <="01000000";
else dout <="00000000";
end if;
end process;
end;
七人表决器 四人以上可以输出P，否则E 可以显示结果
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qrbjq is
port (
set: in std_logic ; ----控制按键
xin: in std_logic_vector ( 6 downto 0 ); ----按键输入表决
sel: out std_logic; ----控制指示灯
xout,xout0,xout1: out std_logic_vector ( 6 downto 0 )
); ----xout显示结果，xout0显示否决的人数，xout1显示赞成的人数
end entity ;
architecture bev of qrbjq is
begin
process ( xin ,set)
variable j: integer :=0;
begin
j:=0;
for i in 0 to 6 loop ------统计同意的个数
if xin(i)='1' then
j:=j+1;
end if;
end loop;
if j>3 then ---判决是否表决通过并输出结果
xout<="0001100"; ---数码管显示P
else xout<="0000110"; ---数码管显示E
end if;
if set='1' then ---是否显示表决比例
sel<='1'; ---显示指示灯亮并且译码输出同意与不同意的数目
case j is ---显示赞成的人数
when 0 =>xout1<="1000000";
when 1 =>xout1<="1111001";
when 2 =>xout1<="0100100";
when 3 =>xout1<="0110000";
when 4 =>xout1<="0011001";
when 5 =>xout1<="0010010";
when 6 =>xout1<="0000010";
when 7 =>xout1<="1111000";
when others =>xout1<="XXXXXXX";
end case;
case j is ---显示不赞成的人数
when 7 =>xout0<="1000000";
when 6 =>xout0<="1111001";
when 5 =>xout0<="0100100";
when 4 =>xout0<="0110000";
when 3 =>xout0<="0011001";
when 2 =>xout0<="0010010";
when 1 =>xout0<="0000010";
when 0 =>xout0<="1111000";
when others =>xout0<="XXXXXXX";
end case;
else ---不显示表决比例
sel<='0';
xout0<="1111111";---不显示数字
xout1<="1111111";
end if;
end process;
end architecture bev;
四七译码器
library ieee;
use ieee.std_logic_1164.all;
entity disp4_7 is
port(d: in std_logic_vector(3 downto 0);
y: out std_logic_vector(6 downto 0));
end disp4_7;
architecture sun of disp4_7 is
begin
process(d)
Begin
case d is
when "0000"=>y<="1111110";
when "0001"=>y<="0110000";
when "0010"=>y<="1101101";
when "0011"=>y<="1111001";
when "0100"=>y<="0110011";
when "0101"=>y<="1011011";
when "0110"=>y<="1011111";
when "0111"=>y<="1110010";
when "1000"=>y<="1111111";
when "1001"=>y<="1111011";
when others=>y<="1000111";
end case;
end process;
end sun;
32位加法分频器 duty 50% （改一个参数就可以改占空比）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32 is
port (clk,rst,en : in std_logic;
cq : out std_logic_vector(5 downto 0);
cout : out std_logic );
end adder32;
architecture sun of adder32 is
signal cout1 :std_logic;
begin
process (clk,rst,en,cout1)
variable cqi :std_logic_vector (5 downto 0);
begin
if rst = '1' then cqi:=(others =>'0');
elsif clk'event and clk='1' then
if en='1' then
if cqi<32 then cqi:=cqi+1;
else cqi:= (others =>'0');
end if;
end if;
end if; -- if cqi>="100011" then cout<=not cout;
if cqi=0 then cout1<='0';
elsif (cqi=16) and (clk'event and clk='1') then cout1<=not cout1;
end if;
cq<=cqi;
cout<=cout1;
end process;
end sun;
八位数据0的个数
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zeronum8 is
port ( xin : in std_logic_vector ( 7 downto 0 );
set : in std_logic;
xout : out integer range 7 downto 0
);
end entity ;
architecture bev of zeronum8 is
begin
process ( xin ,set)
variable j: integer :=0;
begin
if set='1' then
j:=0;
for i in 0 to 7 loop
if xin(i)='0' then --0 numbers
j:=j+1;
end if;
end loop;
end if;
xout<=j;
end process;
end architecture bev;
这里是破解文件，6.0-10.1都可以，里面有详细介绍
Quartus II_6.0-10.1CRACK未改版.rar
(749.89 KB, 下载次数: 193 )
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发表于 2011-4-15 18:21:44
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发表于 2011-5-6 15:24:14
