Digital Noise Emulator for characterization of PLL

angelweishan

Digital Noise Emulator for characterization of phase-locked-loop systems exposed to substrate noise

A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

Yi-Chang Lu

December 2004

Contents

Abstract…….................................................................................................................iii

Acknowledgements.......................................................................................................v

List of Tables ................................................................................................................xiii

List of Figures ...............................................................................................................xv

Chapter 1 Introduction .................................................................................................1

1.1 System-on-a-Chip (SoC)....................................................................................1

1.1.1 Typical Communication Systems ...............................................................1

1.1.2 SoC Applications ........................................................................................2

1.1.3 Reusable Intellectual Property (IP) Blocks.................................................4

1.2 Digital Switching Noise.....................................................................................5

1.3 Previous Work in Substrate Noise .....................................................................7

1.3.1 Different Substrate Types ...........................................................................7

1.3.2 Substrate Models.........................................................................................8

1.3.3 Noise Suppression and Noise-Aware Designs............................................8

1.3.4 Substrate Noise Sensors..............................................................................9

1.3.5 Noise Behavior and Simulation Tools ........................................................10

1.3.6 Circuit Performance under Substrate Noise................................................11

1.3.7 Related Noise Work....................................................................................11

1.4 Outline of Dissertation.......................................................................................12

Chapter 2 Digital Noise Spectra and Digital Noise Emulator .....................................15

2.1 Introduction........................................................................................................15

2.2 Digital Noise Spectra .........................................................................................15

2.2.1 IEEE 802.11a Base-band/MAC Processor .................................................15

2.2.2 Other OFDM Applications .........................................................................19

2.2.3 Spectra in General.......................................................................................20

2.2.4 Key Parameters of Digital Switching Noise ...............................................20

2.3 Digital Noise Emulator ......................................................................................21

2.3.1 Architecture.................................................................................................21

2.3.2 Comparison to Previous Work....................................................................22

2.4 Substrate Noise Sensor ......................................................................................23

2.4.1 Sensor Designs............................................................................................23

2.4.2 Emulated Noise Spectra..............................................................................24

2.5 Summary ............................................................................................................25

Chapter 3 Test Chip Background Information.............................................................27

3.1 Introduction........................................................................................................27

3.2 Test Chip............................................................................................................27

3.2.1 PLL Block...................................................................................................28

3.2.2 Test Board and Measurement Setup ...........................................................30

3.3 Jitter Fundamentals ............................................................................................31

3.3.1 Periodic Jitter ..............................................................................................31

3.3.2 Cumulative Jitter.........................................................................................32

3.4 Measurement Result w/o DSN...........................................................................34

3.5 3-D Histogram Plot............................................................................................35

3.6 Outputs from Spectrum Analyzer ......................................................................36

3.7 Reference Clock Characteristics ........................................................................38

3.8 Summary ............................................................................................................39

Chapter 4 PLL Exposed to Substrate Noise.................................................................41

4.1 Key Parameters Revisited ..................................................................................41

4.2 Periodic Jitter .....................................................................................................42

4.2.1 Phase Impact ...............................................................................................42

4.2.2 Coupling Capacitance .................................................................................43

4.2.3 Switching Activities....................................................................................44

4.2.4 Divider Output ............................................................................................45

4.2.5 Edge Sensitivity ..........................................................................................46

4.2.6 Phase Impact at 40 MHz .............................................................................46

4.2.7 Phase Impact at 160 MHz...........................................................................48

4.2.8 Software Simulation....................................................................................50

4.2.9 Phase Impact at 20, 67, and 133 MHz ........................................................51

4.2.10 Frequency Impact......................................................................................52

4.2.11 DC Impact and Node Sensitivity ..............................................................53

4.3 Cumulative Jitter................................................................................................55

4.3.1 Various Settings ..........................................................................................55

4.3.2 FFT Results.................................................................................................56

4.4 Post-Processing of Periodic Jitter Plots .............................................................59

4.4.1 FFT Plot ......................................................................................................59

4.4.2 Gradient Plots..............................................................................................60

4.5 Summary ............................................................................................................60

Chapter 5 Modeling the Impact of the Substrate .........................................................63

5.1 Introduction........................................................................................................63

5.2 Frequency and Phase Impact .............................................................................63

5.3 Data Format and Types of Models.....................................................................70

5.4 Statistical Model ................................................................................................71

5.5 100 MHz Example .............................................................................................72

5.5.1 Formulation.................................................................................................72

5.5.2 Linear System Model..................................................................................74

5.5.3 Table Format...............................................................................................75

5.5.4 Reconstruction ............................................................................................76

5.6 Summary ............................................................................................................76

Chapter 6 Noise Cancellation ......................................................................................79

6.1 Introduction........................................................................................................79

6.2 Mathematical Model ..........................................................................................79

6.3 Experimental Results .........................................................................................81

6.4 Substrate Noise and Power Grid Noise..............................................................84

6.5 Summary ............................................................................................................87

Chapter 7 Substrate and Line Models..........................................................................89

7.1 Introduction........................................................................................................89

7.2 Substrate Models................................................................................................90

7.2.1 Single Node.................................................................................................90

7.2.2 Fully-Connected Compact Model...............................................................90

7.2.3 Locally Fully-Connected Model .................................................................90

7.2.4 Distributed Model .......................................................................................91

7.2.5 Non-Quasi-Static Distributed Model ..........................................................92

7.3 Inductance Effects..............................................................................................94

7.4 Electromagnetic Substrate Noise .......................................................................95

7.5 Summary ............................................................................................................95

Chapter 8 Conclusion...................................................................................................97

8.1 Recommendation for Future Research...............................................................97

8.2 Conclusion .........................................................................................................99

Appendix A ..................................................................................................................103

A.1 Introduction.......................................................................................................103

A.2 Inductance Calculation......................................................................................103

A.3 Conclusion ........................................................................................................108

Bibliography .................................................................................................................109

rainbowweather

:)

john_123

THANKS

fanjx

好东西 学习

sunjimmy

Very interesting PhD thesis to discuss PLL phenomenon due to impact of substrate noise. The author proposed corresponding behavioral models to mimic the substrate noise impact, and point out future research direction. Unfortunately, no obvious design suggestion is provided to solve this noise impact.

火影忍者

好參考................

火影忍者

保持良好的工作......

lxc531

非常感谢~~

瑜伽

確定主題....

瑜伽

有一點很難理解.......