|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Abstract
A 2.1-to-2.8-GHz low-power consumption all-digital
phase locked loop (ADPLL) with a time-windowed time-to-digital
converter (TDC) is presented. The time-windowed TDC uses
a two-step structure with an inverter- and a Vernier-delay timequantizer
to improve time resolution, which results in low phase
noise. Time-windowed operation is implemented in the TDC, in
which a single-shot pulse-based operation is used for low power
consumption. The test chip implemented in 90-nm CMOS technology
exhibits in-band phase noise of 105 dBc Hz, where the
loop-bandwidth is set to 500 kHz with a 40-MHz reference signal,
and out-band noise of 115 dBc Hz at a 1-MHz offset frequency.
The chip core occupies 0.37 mm􀀀 and the measured power consumption
is 8.1 mA from a 1.2-V power supply.
abbr_c2e7353a8baea2805851b78bbd66a5b0.pdf
(1.5 MB, 下载次数: 425 )
|
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2011-1-31 10:51:31
