synthesizable SDRAM controller Core--verilog

kevinwjs

//*******************************************************************************
//  S Y N T H E S I Z A B L E      S D RA M     C O N T R O L L E R    C O RE
//
//  This core adheres to the GNU Public License  
//
//  This is a synthesizable Synchronous DRAM controller Core.  As it stands,
//  it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz
//  and 125MHz. For example: Samsung KM432S2030CT,  Fujitsu MB81F643242B.
//
//  The core has been carefully coded so as to be "platform-independent".  
//  It has been successfully compiled and simulated under three separate
//  FPGA/CPLD platforms:
//      Xilinx Foundation Base Express V2.1i
//      Altera Max+PlusII V9.21
//      Lattice ispExpert V7.0
//  
//  The interface to the host (i.e. microprocessor, DSP, etc) is synchronous
//  and supports ony one transfer at a time.  That is, burst-mode transfers
//  are not yet supported.  In may ways, the interface to this core is much
//  like that of a typical SRAM.  The hand-shaking between the host and the
//  SDRAM core is done through the "sdram_busy_l" signal generated by the
//  core.  Whenever this signal is active low, the host must hold the address,
//  data (if doing a write), size and the controls (cs, rd/wr).  
//

verilog_SDRAM_core.rar (27.76 KB, 下载次数: 387 )

2011-1-24 13:46 上传

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qptom

thanks!

zh123456789

谢谢啊

dubu113

thank you very much

puyuwei

谢谢分享！

smartwang

看看.

King8027

正需要，谢谢楼主！

jefffree

lihai

roger24

thanks! 正需要，谢谢楼主！

tom0626

如果早看到這 IP ，我就不用自己設計一個 sdram controller。下載下來研究，再來討論切磋。