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发表于 2011-2-1 13:22:09
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fuyibin兄讲的有道理,过年啦,还不放假呀!
是不是65nm的2.5V故意做得有点特殊,所以也能承受 ...
goodsilicon 发表于 2011-2-1 11:55
这个东西我比较过,65nm的2.5V device好像没什么特殊的, tox大概5nm的样子
通常来说每个工艺节点都有自己的标准,0.35um tox=7nm, 0.25um tox=5nm, 0.18um tox=4nm,
0.13um/90nm/65nm的低压device tox通常都是2nm+和2nm,到40nm也还是维持在2nm左右,可能都有high K了
我自己弄了表,有兴趣可以看看 | | tox_nmos (nm) | tox_pmos (nm) | CSMC 0.5um | | 12.7 | 12.7 | SMIC 0.18um | 1.8V device
n18/p18 | 3.87 | 3.74 | | 3.3V device
n33/p33 | 6.65 | 6.62 | SMIC 0.13um | 1.2V device
n12/p12 | 2.58 | 2.52 | | 3.3V device
n33/p33 | 7 | 7 | | 1.0V device
n10/p10 | 2 | 2.2 | SMIC 90nm | 1.8V device
n18/p18 | 3.32 | 3.44 | | 3.3V devcie
n33/p33 | 7.1 | 7.23 | TSMC 0.35um | 3.3V device | 7.6 | 7.6 | TSMC 0.25um | 2.5V device | 5.4 | 5.4 | | 3.3V device | 7.1 | 7.1 | TSMC 65nm | 1.0V device | 2.07 | 2.3 | | 2.5V device | 5.6 | 5.9 | AMI 1.0um | | 15.5 | 15.5 | AMI 1.6um | | 30.7 | 30.7 | UMC 0.5um | | 13.5 | 13.5 | UMC 0.35um | 3.3V device | 7 | 7 | | 5V device | 12 | 12 | UMC 0.25um | 2.5V device | 5.5 | 5.5 | HHNEC 0.35um | | 15.5 | 15.5 |
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