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为什么modulator freq不能高过PFD freq? Quantization noise increase?
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 The D-S modulators for the fractional-N synthesizer may not use the decimation filter to suppress the high-frequency noise in the digital domain since the PLL with integer-N dividers does not allow an intermediate level between N and N + 1. Therefore, the clock frequency of the oversampling modulator must be same as the phase detector frequency in order to not increase the quantization noise.?????
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