FPGA/CPLD设计无复位输入，内部寄存器初值是怎样的？

cxa

Registers in the device core always power up to a low (0) logic level on all Altera
devices. If your design specifies a power-up level other than 0, synthesis tools can
implement logic that causes registers to behave as if they were powering up to a high
(1) logic level.