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Abstract—Recent research at Intel suggests that chips with hundreds
of processor cores are possible in the not-so-distant future.
As the number of cores grows, so does the size of the cache systems
required to allow them to operate efficiently. Caches have grown
to consume a significant percentage of the power utilized by a processor.
In this research, we extend the concept of location cache to
support chip multiprocessors (CMPs) systems in combination with
low-power L2 caches based upon the gated-ground technique. The
combination of these two techniques allows for reductions in both
dynamic and leakage power consumption. In this paper, we will
present an analysis of the power savings provided by utilizing location
caches in a CMP system. The performance of the cache system
is evaluated by extending the capability ofCACTI and Simics using
the SPLASH-2 and ALPBench benchmark suites. These simulation
results demonstrate that the utilization of location caches in
CMP systems is capable of saving a significant amount of power
over equivalent CMP systems that lack location caches.
05286241.pdf
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发表于 2011-1-7 09:57:02
