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本帖最后由 hslinkstar 于 2010-12-26 06:38 编辑
現任UCLA的Professor (http://www.ee.ucla.edu/~ckygroup/)
Abstract
Demand for bandwidth in serial links has been increasing as the communications
industry demand higher quantity and quality of information. Whereas traditional gigabit
per second links has been in bipolar or GaAs, this research aims to push the use of CMOS
process technology in such links. Intrinsic gate speed limitations are overcome by
parallelizing the data. The on-chip frequency is maintained at a fraction (1/16) of the offchip
data rate. Clocks with carefully controlled phases tapped from a local ring oscillator
are driven to a bank of input samplers to convert the serial bit stream into parallel data.
Similarly, the overlap of multiple-phased clocks are used to synchronize the multiplexing
of the parallel data onto the transmission line. To perform clock/data recovery, data is
further oversampled with finer phase separation and passed to digital logic. The digital
logic operates upon the samples to detect transitions in the bit stream to track the bit
boundaries. This tracking can operate at the cycle rate of the digital logic allowing
robustness to systematic phase noise. The challenge lies in the capturing of the high
frequency data stream and generating low jitter, accurately spaced clock edges. A test chip
is built demonstrating the transmission and recovery of a 4.0-Gb/s bit streams with < 10-14
bit-error rate using a 3x oversampled system in a 0.5-mm MOSIS CMOS process.
(1998.12)[Chil-Kong Ken Yang]DESIGN OF HIGH-SPEED SERIAL LINK IN CMOS.pdf
(2.04 MB, 下载次数: 237 )
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发表于 2010-12-26 06:37:07
