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Requisition Description
The candidate will be responsible for Low power flatten UPF/Hier UPF flow's development and comprehensive advanced feature testing of Synopsys IC Compiler low power part. Good knowledge of Backend/Frontend design methodologies. Know low power cell -- level shift/ISO/AO cells’ function and UPF/CPF rule. and the candidate should be able to develop tools/scripts to constantly improve testing process efficiency and product quality.
BS with 5+ years of relevant experience, MS with 3+ years of relevant experience, or related Ph.D. with 1+ years of experience. Strong communication. Proficient low power UPF design methodology and a strong understanding of ASIC design flows .Knowledge in low power part, UPF/CPF is highly desired. Knowledge in the areas of Place, CTS ,Timing or Route is a plus
有意者请发简历到 aspc1234@yahoo.com.cn
地点在上海中山公园 |
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