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本帖最后由 qjlee 于 2010-11-19 14:26 编辑
1.A fast locking charge-pump PLL with adaptive bandwidth
2.A novel charge pump PLL with reduced jitter characteristics
3.A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking
4.All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs
5.Analysis of a charge-pump PLL a new model
6.Analysis of third-order charge pump PLL
7.Behavioral Model based Simulation Methods for Charge-Pump PLL's
8.Behavioural analysis of charge-pump PLL's
9.Design and Analysis Of Clock Recovery System For Digital Vcr From Baseband EFM Transmission With Charge Pump PLL
10.DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1
11.Genetic optimization of charge-pump PLL parameters
12.Investigations for minimum invasion digital only built-in ramp based test techniques for charge pump PLL s
13.Multi-layer behavioral modeling of charge-pump phase-locked loops
14.Optimum phase-acquisition technique for charge-pump PLL
15.Phase Accuracy of Charge Pump PLL's
16.Pump current modulated charge pump PLL |
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