[ebook]The Power of Assertions in SystemVerilog

pipiw · 发表于 2010-11-17 10:37:41

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本帖最后由 pipiw 于 2010-11-17 13:10 编辑

[size=120%]The Power of Assertions in SystemVerilog
By Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny

Publisher: Springer
Number Of Pages: 544
Publication Date: 2010-10-22
ISBN-10 / ASIN: 1441965998
ISBN-13 / EAN: 9781441965998

Product Description:

This book provides a deeper understanding of the meaning of the enhancements contained in the new SystemVerilog 1800-2009 LRM. In particular, it discusses the context of practical deployment in hardware design projects. The material also addresses language implementation alternatives and their impact on simulation performance as well as the ability to debug them in simulation and formal verification environments. The underlying performance issues are illustrated for practical examples drawn from the author's experience.

mtwumtwu · 发表于 2010-11-17 11:10:12

good reference for hardware design

zh123456789 · 发表于 2010-11-17 18:25:31

谢谢啊

qptom · 发表于 2010-11-17 19:44:37

thanks!

wangzt · 发表于 2010-11-17 19:45:59

回复 1# pipiw

多谢多谢

hhjankin · 发表于 2010-11-17 19:53:48

great book!

Daniel10003 · 发表于 2010-11-17 21:21:45

呵呵，谢谢楼主的分享

wenxiao925 · 发表于 2010-11-17 21:25:24

谢谢分享，也许以后能用得上

iseesky · 发表于 2010-11-20 16:47:27

good!thanks!

wlrzb10 · 发表于 2010-12-1 22:04:59

谢谢分享，希望以后能用得上

[资料] [ebook]The Power of Assertions in SystemVerilog

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