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[原创] 请教怎样驱动型号为TCD1206的CCD?

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发表于 2010-11-15 22:23:52 | 显示全部楼层 |阅读模式
10资产
波形如下:

波形2.jpg
发表于 2011-12-28 21:38:13 | 显示全部楼层
reg [5:0] cnt6;
wire f_base_clk1;  //1MHZ
reg f_r1;
//--------
parameter DIV_CLK_CNT = 49;
parameter DIV_CLK_GE_CNT = (DIV_CLK_CNT+1)/2-1;
//--------
always @(posedge clk)
if(cnt6==DIV_CLK_CNT)
cnt6<=0;
else
cnt6<=cnt6+1;

always @(posedge clk)
if(cnt6<=DIV_CLK_GE_CNT)
f_r1<=0;
else
f_r1<=1;

assign f_base_clk1=f_r1; //1MHZ
//----------------------
//-------- generate rs,cp-----------//
reg [9:0] cnt_rs;
reg rs_r1,cp_r1;
//--------
//RS_2_TIME = RS_1_TIME+4
//CP_2_TIME = CP_1_TIME+4
//CP_1_TIME = RS_2_TIME+1
parameter RS_1_TIME = 13;
parameter RS_2_TIME = RS_1_TIME+4;
parameter CP_1_TIME = RS_1_TIME+5;
parameter CP_2_TIME = RS_1_TIME+9;
//--------
always @(posedge clk)
if(ccd_control==0)
cnt_rs<=0;
else if(f_base_clk1)
cnt_rs<=cnt_rs+1;
else
cnt_rs<=0;

always @(posedge clk)
if(rs_cp_control1==1)
rs_r1<=0;
else
if(cnt_rs>=RS_1_TIME && cnt_rs<=RS_2_TIME)
rs_r1<=1;
else
rs_r1<=0;

always @(posedge clk)
if(rs_cp_control1==1)
cp_r1<=0;
else
if(cnt_rs>=CP_1_TIME && cnt_rs<=CP_2_TIME)
cp_r1<=1;
else
cp_r1<=0;
//------------------------
//-------- generate sh--------------//
reg [25:0] cnt_int_time1_r;
//-------
//积分时间级别
reg [25:0] cnt_int_time1_1;
reg [25:0] cnt_int_time1_2;
reg [25:0] cnt_int_time1_3;
reg [25:0] cnt_int_time1_4;
reg [25:0] cnt_int_time1_5;
reg [25:0] cnt_int_time1_6;
reg [25:0] cnt_int_time1_7;
reg [25:0] cnt_int_time1_8;
reg [25:0] cnt_int_time1_9;
//------------
reg sh_r1;
//---------------------------
//积分时间级别1
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_1<=0;
else
if(cnt_int_time1_1==105124)  //integrated time = 2100*1000ns
cnt_int_time1_1<=0;
else
cnt_int_time1_1<=cnt_int_time1_1+1;
//积分时间级别2
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_2<=0;
else
if(cnt_int_time1_2==130124)  //integrated time = 2600*1000ns
cnt_int_time1_2<=0;
else
cnt_int_time1_2<=cnt_int_time1_2+1;
//积分时间级别3
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_3<=0;
else
if(cnt_int_time1_3==155124)  //integrated time = 3100*1000ns
cnt_int_time1_3<=0;
else
cnt_int_time1_3<=cnt_int_time1_3+1;
//积分时间级别4
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_4<=0;
else
if(cnt_int_time1_4==180124)  //integrated time = 3600*1000ns
cnt_int_time1_4<=0;
else
cnt_int_time1_4<=cnt_int_time1_4+1;
//积分时间级别5
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_5<=0;
else
if(cnt_int_time1_5==205124)  //integrated time = 4100*1000ns
cnt_int_time1_5<=0;
else
cnt_int_time1_5<=cnt_int_time1_5+1;
//积分时间级别6
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_6<=0;
else
if(cnt_int_time1_6==230124)  //integrated time = 4600*1000ns
cnt_int_time1_6<=0;
else
cnt_int_time1_6<=cnt_int_time1_6+1;
//积分时间级别7
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_7<=0;
else
if(cnt_int_time1_7==255124)  //integrated time = 5100*1000ns
cnt_int_time1_7<=0;
else
cnt_int_time1_7<=cnt_int_time1_7+1;
//积分时间级别8
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_8<=0;
else
if(cnt_int_time1_8==280124)  //integrated time = 5600*1000ns
cnt_int_time1_8<=0;
else
cnt_int_time1_8<=cnt_int_time1_8+1;
//积分时间级别9
always @(posedge clk)
if(ccd_control==0)
cnt_int_time1_9<=0;
else
if(cnt_int_time1_9==305124)  //integrated time = 6100*1000ns
cnt_int_time1_9<=0;
else
cnt_int_time1_9<=cnt_int_time1_9+1;
//------------------------------
//----------------
parameter CNT_SH_TIME1 = CNT_INT_TIME1+25;
parameter CNT_SH_TIME2 = CNT_INT_TIME2-25;
//----------------
always @(posedge clk)
if(cnt_int_time1_r>=CNT_SH_TIME1 && cnt_int_time1_r<=CNT_SH_TIME2)
sh_r1<=1;
else
sh_r1<=0; //generate sh

//---------------------------------
reg rs_cp_control1;
//-----------------
parameter CNT_INT_TIME1 = 25; ///////////////////////////////user change//////////////////////////////////
parameter CNT_INT_TIME2 = CNT_INT_TIME1+124;
//-----------------
//-----------------
always @(posedge clk)
if(cnt_int_time1_r>=CNT_INT_TIME1 && cnt_int_time1_r<=CNT_INT_TIME2)
rs_cp_control1<=1;
else
rs_cp_control1<=0; //generate rs_cp_control
//--------------------------------
//-------- generate f1,f2--------------------//
reg f1_r1,f2_r1;

always @(posedge clk)
if(ccd_control==0)
begin
  f1_r1<=0;
  f2_r1<=0;
end
else
if(rs_cp_control1)
begin
  f1_r1<=1;
  f2_r1<=0;
end
else
begin
  f1_r1<=f_r1;
  f2_r1<=~f_r1;
end
//---------------------------------------------
wire [8:0] sel;
//-----------
parameter INT_TIME_LEVEL = 9'b1000_0000_0;///////////////////////////////user change//////////////////////////////////
//-----------
always @(sel)
case(sel)
  9'b0000_0000_1: begin
                    cnt_int_time1_r<=cnt_int_time1_1;
                  end
  9'b0000_0001_0: begin
                    cnt_int_time1_r<=cnt_int_time1_2;
                  end
  9'b0000_0010_0: begin
                    cnt_int_time1_r<=cnt_int_time1_3;
                  end
  9'b0000_0100_0: begin
                    cnt_int_time1_r<=cnt_int_time1_4;
                  end
  9'b0000_1000_0: begin
                    cnt_int_time1_r<=cnt_int_time1_5;
                  end
  9'b0001_0000_0: begin
                    cnt_int_time1_r<=cnt_int_time1_6;
                  end
  9'b0010_0000_0: begin
                    cnt_int_time1_r<=cnt_int_time1_7;
                  end
  9'b0100_0000_0: begin
                    cnt_int_time1_r<=cnt_int_time1_8;
                  end
  9'b1000_0000_0: begin
                    cnt_int_time1_r<=cnt_int_time1_9;
                  end
         default: begin
                    cnt_int_time1_r<=cnt_int_time1_1;
                  end
endcase

assign sel=INT_TIME_LEVEL;
//-----------------------------
assign f1=~f1_r1;
assign f2=~f2_r1;
assign sh=~sh_r1;
assign rs=~rs_r1;
assign cp=~cp_r1;
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