|
|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
这是我搜索资料时陆续收集到的外国大学电子课程的资料。都是手动一个一个下载，然后打包，希望对大家有所帮助。PS：虽然全是英文，但是对于工程师来说，应该不是大问题
如果反应良好，我将再上传一部High-Speed Memory Systems，很经典的课程，包括各种参考资料也都齐全。
课程一：Digital Design
Objectives
In this course, students will learn to use a hardware description language (Verilog) in the
digital design process. Emphasis will be on system level concepts and high-level design
representations. Methods will be learned that are appropriate for use in automated
synthesis systems. Students will have the opportunity to use a commercial computer
aided engineering (CAE) tool to design a series of increasingly complex devices.
Students will also have the opportunity to use a commercial synthesis tool to
automatically map high-level descriptions to Field Programmable Gate Arrays (FPGAs).
ECE 4514 Digital Design II.part1.rar
(2.86 MB, 下载次数: 13 )
ECE 4514 Digital Design II.part2.rar
(2.86 MB, 下载次数: 12 )
ECE 4514 Digital Design II.part3.rar
(1.09 MB, 下载次数: 12 )
课程二：Advanced Digital Design with Hardware Description Languages
Topics:
1. Review of Combinational and Sequential Digital Logic Design
2. Basic Verilog Language Structures (Datatypes, Modules, etc.)
– Datatypes: nets, registers, event, bitvectors, arrays, parameters
– Modules: ports, hierarchical names
3. Structural and Behavioral Specifications
– Basic gates, User-defined primitives, Modeling levels
– Synthesizable operations, Continuous assignments (Examples: Adders, ALU)
4. Simulation. Testbenches and debugging.
5. Synthesis flow. Synthesis to Standard cells and FPGA.
6. Procedural Specifications and Designing Single Modules
– The always block
– Functions and Tasks
– Blocking and Non-blocking assignments
– Control constructs and their Synthesis
– Design examples: Counters, Unsigned Multiplier
– Validation: Verification Vectors, Testbench Coding Approaches, Post-synthesis verification
7. Finite State Machine Specifications and Styles
– Explicit and Implicit Specification Styles
– Example: Booth multiplier
– Example: First-in-First-Out buffer (FIFO)
8. Design Reuse
– Instantiation of parametrized modules.
– Control-point style for design reuse (Examples with FIFO)
– Using vendor components (Booth multiplier)
9. Improving Timing, Area, and Power
– Delay calculations
– Timing design with Flip-flops and Latches
– Low-power design issues and Area considerations.
Advanced Digital Design with HDL.part1.rar
(2.86 MB, 下载次数: 19 )
Advanced Digital Design with HDL.part2.rar
(2.86 MB, 下载次数: 17 )
Advanced Digital Design with HDL.part3.rar
(2.86 MB, 下载次数: 18 )
Advanced Digital Design with HDL.part5.rar
(825.82 KB, 下载次数: 19 )
Advanced Digital Design with HDL.part4.rar
(2.86 MB, 下载次数: 17 )
课程三：Secure Hardware Design
Objectives
This course covers design and implementation of secure hardware at multiple levels of
abstraction, including cryptographic hardware primitives, cryptographic modules, and
trusted platforms. The course also addresses reverse engineering of cryptographic
modules using passive attacks, active attacks, cryptanalytic techniques, and
countermeasures against reverse engineering. The course uses case studies and literature
surveys to reflect on the state-of-the-art in secure hardware implementation.
Cryptography theory is covered on an as-needed basis.
Secure Hardware Design.part1.rar
(2.86 MB, 下载次数: 9 )
Secure Hardware Design.part2.rar
(2.86 MB, 下载次数: 7 )
Secure Hardware Design.part3.rar
(2.86 MB, 下载次数: 8 )
Secure Hardware Design.part4.rar
(2.86 MB, 下载次数: 8 )
Secure Hardware Design.part5.rar
(2.86 MB, 下载次数: 8 )
Secure Hardware Design.part6.rar
(1.86 MB, 下载次数: 7 )
|
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-11-3 13:24:12
