编了一个switch的vhdl程序，欢迎指正！

jerrymeng

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY switch IS
  PORT (CE,CLK: IN STD_LOGIC;
        DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        DOUT: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END switch;
ARCHITECTURE switch_arch OF switch IS
SIGNAL indata:IN BIT;
BEGIN
indata<=CE
F1ROCESS(CLK)            
BEGIN
   IF(CLK'EVENT AND CLK='1')THEN
     CASE indata IS
     WHEN "0" => DOUT(7 DOWNTO 0) <= DIN;
     WHEN "1" => DOUT(15 DOWNTO 8) <=DIN;
     END CASE;
   END IF;
END PROCESS F1;
END switch_arch;