判断一个数能否被3整除的电路（附Verilog代码）

guoyu · 发表于 2010-9-30 09:41:37

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本帖最后由 guoyu 于 2010-10-1 11:27 编辑

Well, it generates a circuit detecting if the input (unsigned 8bit number range [0,255])
can be divided by 3 (can be easily modified to 5,7,etc.) evenly.
If yes, a flag (1 clk cycle) will appear.

Of course one can use modulo ('%' in verilog) to implement the function,
but the cost may be higher.

Consider A = 4'b1011, which is 11 in decimal, let's do this:
X[0] == 2^0 = 1; 1%3 = 1; so there is a 1.
X[1] == 2^1 = 2; 2%3 = 2; so there is a 2.
X[2] == 2^2 = 4; 4%3 = 1; so there is a 1.
X[3] == 2^3 = 8; 8%3 = 2; so there is a 2.

Let's add the due remainders up, which is
A[0]*X[0] + A[1]*X[1] + A[2]*X[2] + A[3]*X[3] = 5,
and 5 is not a multiple of 3.

Try 4'b0011 or 4'b1111, you will see it.

If you have a better solution (in terms of RTL implementation), do tell me!
I hereby thank you in advance.

Guo Yu

module div3
( input clk,
input rst_n,
input [7:0] data,
output reg flag
);
reg [3:0] sum;
integer i;
always @ *
begin
sum = 0;
for (i=0;i<8;i=i+1)
begin
if (i==0 || i==2 || i==4 || i==6 )
sum = (data[i]) ? sum + 1 : sum;
else
sum = (data[i]) ? sum + 2 : sum;
end
end
always @ (posedge clk, negedge rst_n)
begin
if (!rst_n)
flag <= 1'b0;
else if (sum ==0 || sum ==3 || sum==6 || sum==9 || sum==12)
flag <= 1'b1;
else
flag <= 1'b0;
end
endmodule;

复制代码

源码和Testbench：

div3.rar (1.29 KB, 下载次数: 30 )

wushiqiang · 发表于 2010-9-30 11:23:46

有没有时序输入每比特判断的例子。

guoyu · 发表于 2010-9-30 11:31:41

回复 2# wushiqiang

加个移位寄存器吧。把串行的数据转换成并行再比较。可以参考网上的一片不错的帖子：http://www.cnblogs.com/oomusou/archive/2009/10/24/p2s_s2p.html

wjdz · 发表于 2010-9-30 11:33:53

My stduy is just at the beginning, and study hard to know the Verilog language

guoyu · 发表于 2010-9-30 11:35:13

回复 4# wjdz

Just work hard on it. You will find it is very useful.

guoyu · 发表于 2010-10-1 11:27:43

增加了Testbench.

zhang2000 · 发表于 2010-10-1 21:00:58

给你改进一下，每两个bit  进行组合译码
X[7] X[6] 分成一组
X[5] X[4] 分成一组
X[3] X[2] 分成一组
X[1] X[0] 分成一组

如下  真值表
X[2*n+1] X[2*n]       OUTn（两bit）
0             0             0
   0             1             1
   1             0             2
   1             1             0

然后  OUT0 + OUT1 + OUT2 + OUT3得出结果，再按同样算法来一遍

四位组合应该能比两位组合要优化一些

wushiqiang · 发表于 2011-5-18 21:55:50

很好下来学习一下

北极鸟 · 发表于 2011-6-2 00:55:52

学习一下.....

haonan · 发表于 2011-6-10 19:55:19

好东西，谢谢

[原创] 判断一个数能否被3整除的电路（附Verilog代码）

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