latch 对dft的影响

tzl123 · 发表于 2011-1-18 14:49:37

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wind1272 · 发表于 2011-2-16 00:14:33

由於ＤＦＴＣ做compile -scan時會將ＦＦ用scan FF取代
但latch沒有cell可以取代
因此對ＤＦＴ會有影響，如果無法控制與觀察的話，會降低test coverage
另外latch在ＳＴＡ時分析也也會有些影響

jasonL · 发表于 2011-2-20 16:28:07

When u are doing ASIC design, latch is not prefer during gate simulation or called synthesis. U have to initialize all the registers at every block for designing combinational logic. And that is rule of thumb...

jasonL · 发表于 2011-2-20 16:31:38

therefore, d flip-flop is often used in ASIC design, but there is a trade-off, d flip-flop is required more area than data latch...

eecc · 发表于 2011-2-27 01:21:56

剛好也想知道這方面的資訊啊

skjeon78 · 发表于 2016-1-24 14:37:12

thanks a lot.

[原创] latch 对dft的影响

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