modelsim仿真DCM问题

plivm

由于自动生成的.Fdo文件中缺少类似vlog +acc  "BUFG.v"的语句，BUFG是通过ipcore生成的模块，这时只需要在modelsim中的控制台输入vlog +acc  "BUFG.v"回车，就可以识别到ipcore的module了（也可以考虑直接修改.fdo文件，但是我的ise版本好像设置不能修改.fdo文件，修改后就不能在modelsim中运行了），然后重新仿真就行了。

另外解决方法：

1.这个可以在modelsim中建立一个工程，把ise的工程加入，从modelsim中仿真而不通过ise。

ourdoctor

我做modelsim仿真时候DCM也处问题了，请大家帮忙分析一下原因：
vsim -L simprims_ver -L unisim_ver -L xilinxcorelib_ver -novopt DDPS.test_TopDesign
# vsim -L simprims_ver -L unisim_ver -L xilinxcorelib_ver -novopt DDPS.test_TopDesign
# Loading DDPS.test_TopDesign
# Loading DDPS.TopDesign
# ** Warning: (vsim-3010) [TSCALE] - Module 'TopDesign' has a `timescale directive in effect, but previous modules do not.
#         Region: /test_TopDesign/td
# Loading unisim_ver.DCM
# Loading DDPS.TrapezoidalShaping
# Loading DDPS.FIFO
# Loading xilinxcorelib_ver.FIFO_GENERATOR_V6_2
# Loading DDPS.TDRAM
# Loading xilinxcorelib_ver.BLK_MEM_GEN_V4_2
# Loading xilinxcorelib_ver.BLK_MEM_GEN_V4_2_mem_module
# Loading xilinxcorelib_ver.BLK_MEM_GEN_V4_2_output_stage
# Loading xilinxcorelib_ver.BLK_MEM_GEN_V4_2_softecc_output_reg_stage
# Loading DDPS.SpectrumForming
# Loading DDPS.FT245BL
# Loading DDPS.ReadTDRAM_AndSend
# Loading DDPS.Data_Receive
# Loading unisim_ver.dcm_clock_divide_by_2
# Loading unisim_ver.dcm_maximum_period_check
# Loading unisim_ver.dcm_clock_lost
# Loading xilinxcorelib_ver.fifo_generator_v6_2_bhv_ver_as
# ** Warning: (vsim-3017) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Too few port connections. Expected 15, found 5.
#         Region: /test_TopDesign/td
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'LED1'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'LED2'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'LED3'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'LED4'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'ADC_PDWN'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'ADC_CLK'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'DAC_DATA'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'DAC_CLK'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'USB_WR'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/testbench-top.v(11): [TFMPC] - Missing connection for port 'USB_RD'.
# ** Warning: (vsim-3017) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Too few port connections. Expected 19, found 7.
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLKIN_IN' not found in the connected module (1st connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLKFX_OUT' not found in the connected module (2nd connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLKIN_IBUFG_OUT' not found in the connected module (3rd connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLK0_OUT' not found in the connected module (4th connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLK2X_OUT' not found in the connected module (5th connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'CLK2X180_OUT' not found in the connected module (6th connection).
#         Region: /test_TopDesign/td/DCM1
# ** Error: (vsim-3063) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): Port 'LOCKED_OUT' not found in the connected module (7th connection).
#         Region: /test_TopDesign/td/DCM1
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK0'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK180'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK270'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK2X'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK2X180'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLK90'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLKDV'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLKFX'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLKFX180'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'LOCKED'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'PSDONE'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'STATUS'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLKFB'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'CLKIN'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'DSSEN'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'PSCLK'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'PSEN'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'PSINCDEC'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(72): [TFMPC] - Missing connection for port 'RST'.
# ** Warning: (vsim-3017) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(229): [TFMPC] - Too few port connections. Expected 14, found 12.
#         Region: /test_TopDesign/td/ft245
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(229): [TFMPC] - Missing connection for port 'RD_Success'.
# ** Warning: (vsim-3722) E:/Eapp/EDA/ModelSim/testsrc/TopDesign.v(229): [TFMPC] - Missing connection for port 'LED'.
# Error loading design

zhangkangdouble

顶一个

reacherone

经过在project添加optimization configuration之后解决了问题

lxt1020

直接在代码中把它改成符合要求的就行。