RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE All Digital PLL & DLL

angelweishan

RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE ALL-DIGITAL PHASE-LOCKED AND DELAY-LOCKED LOOPS

Chapter 1 – Introduction ………………………………………………………………… 1

Chapter 2 – Phase-Locked Loop Basics ………………………………………………… 7
2.1. Basic Operations of a PLL ……………………………………………………. . 7
2.2. Building Blocks of a PLL ……………………………………………………... 9
2.2.1. Phase Detector ………………………………………………………… 10
2.2.2. Loop Filter ……………………………………………………………. . 18
2.2.3. Voltage-Controlled Oscillator (VCO) ………………………………… 20
2.3. System Analysis of a second-order PLL ……………………………………... 24
2.4. A new candidate – Delay-Locked Loop ……………………………………... 28

Chapter 3 – Loop Dynamics and Jitter ………………………………………………… 31
3.1. Tracking and Acquisition ……………………………………………………. . 31
3.1.1. Tracking ………………………………………………………………. . 32
3.1.2. Acquisition ……………………………………………………………. 36
3.1.3. Aided Acquisition ……………………………………………………... 40
3.2. Phase Noise and Jitter ………………………………………………………... 41
3.2.1. Noisy Input – External Jitter …………………………………………. . 42
3.2.2. Noise in the Oscillator – Internal Jitter ………………………………. . 46

Chapter 4 – Charge-Pump and All-Digital Loops …………………………………….. 53
4.1. Charge-Pump Phase-Locked Loops …………………………………………. . 53
4.1.1. Charge-Pump Basics …………………………………………………. . 54
4.1.2. Self-Bias Techniques …………………………………………………. . 59
4.1.3. Dead-zone ……………………………………………………………... 61
4.1.4. Charge-sharing ………………………………………………………... 63
4.2. All-Digital Loops ……………………………………………………………. . 65
4.2.1. All-Digital Building Blocks …………………………………………... 65
4.2.2. Design Criteria of All-Digital Loops …………………………………. . 71
4.2.3. Delay Interpolation ……………………………………………………. 72

Chapter 5 -- An All-Digital DLL using the Symmetrical Delay Line ………………… 75
5.1. Synchronization in the Memory System ……………………………………... 75
5.2. Register-Controlled Symmetrical Delay Line (RSDL) ………………………. 77
5.3. An All-Digital DLL using the RSDL ………………………………………… 80
5.3.1. System Considerations ………………………………………………... 80
5.3.2. Circuits Design ………………………………………………………... 83
5.3.3. Experiment Results ……………………………………………………. 86
5.4. Phase Shifter and Register-Controlled Oscillator ……………………………. 89

Chapter 6 – An All-Digital PLL based on Register-controlled Oscillator …………… 91
6.1. Design an All-Digital PLL …………………………………………………… 91
6.2. Two-Loop Register-Controlled Oscillator (RCO) …………………………… 92
6.2.1. Frequency Granularity of the RCO …………………………………… 93
6.2.2. Two-Loop Architecture ………………………………………………. . 96
6.2.3. Circuit Design …………………………………………………………. 99
6.3. Design the RCO-Based ADPLL ……………………………………………. 100
6.3.1. Hierarchy Pull-in ……………………………………………………. . 102
6.3.2 Coarse Loop …………………………………………………………. . 107
6.3.3. All-Digital PFD ……………………………………………………… 109
6.3.4. Fine Loop ……………………………………………………………. 112
6.3.5. Locking Mechanism in the Fine Loop ………………………………. 116
6.4. Loop Dynamics of the RCO-Based ADPLL ………………………………. . 119
6.4.1. Step-in Phase Response ……………………………………………… 119
6.4.2. Step-in Frequency Response ………………………………………… 120
6.4.3. Limit Handling ………………………………………………………. 123
6.4.4. Locking Characteristics with Variations ……………………………. . 125
6.5. Experimental Results ………………………………………………………. . 128

Chapter 7 – Conclusion ……………………………. ...................................................... 134
Bibliography ..................................................................................................................... 136

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