ESD devices mechnism

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ON HIGH INJECTION MECHANISMS Semiconductor Devices under ESD Conditions.pdf (3.34 MB , 下载次数: 71 )

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Gianluca Boselli 2001 dessis.

Contents
Chapter 1 Electrostatic Discharge Phenomenology........................................... 1
1.I Problem description: what is ESD? .................................................................... 2
1.II On-chip protection against ESD: principles and devices ................................ 3
1.II.a ggnMOSt’s....................................................................................................... 4
1.II.b Silicon controlled rectifier (SCR) ....................................................................... 6
1.II.c Lateral npn...................................................................................................... 7
1.II.d Diodes.............................................................................................................. 8
1.II.e Protection networks........................................................................................... 8
1.III Testing ESD protection elements: how robust are they? ................................ 9
1.III.a Human Body Model (HBM) ........................................................................... 9
1.III.b Machine Model (HBM)................................................................................. 10
1.III.c Charged Device Model (CDM) ...................................................................... 10
1.III.d Square pulse testing ........................................................................................ 10
1.IV EOS/ESD induced failure mechanisms and criteria...................................... 11
1.IV.a Junction burnout............................................................................................. 11
1.IV.b Metallization burnout..................................................................................... 12
1.IV.c Oxide breakdown........................................................................................... 12
1.IV.d Leakage current as failure criterion ................................................................. 12
1.V Motivation of the work....................................................................................... 13
1.VI Thesis outline ....................................................................................................... 14
1.VII References ............................................................................................................ 16
Chapter 2 High Injection Basics in Semiconductors....................................... 19
2.I One type carrier injection................................................................................... 20
2.I.a Current in a system without thermal free carriers ............................................. 21
2.I.b Current in a system with thermal free carriers .................................................. 23
2.I.c Current in a system with thermal free carriers and traps................................... 25
2.II Two-carrier currents............................................................................................ 26
2.II.a The semiconductor injected plasma................................................................... 27
2.III Analytical approach to injection in semiconductors....................................... 29
2.III.a Low injection level .......................................................................................... 33
2.III.b High injection level ......................................................................................... 33
2.IV Numerical approach to injection in semiconductors...................................... 34
2.IV.a The Poisson Equation .................................................................................... 34
2.IV.b The Continuity Equations.............................................................................. 35
2.IV.c Current Relations........................................................................................... 36
2.IV.d Mobility ......................................................................................................... 36
2.IV.e Heat Conduction Equation ............................................................................ 37
2.IV.f Thermally generated carriers............................................................................ 38
2.V Conclusions.......................................................................................................... 39
2.VI References ............................................................................................................ 39
Chapter 3 Diffused Resistors under High Injection Conditions .................. 41
3.I Introduction ......................................................................................................... 42
3.II Region 1: Linear regime...................................................................................... 44
3.III Region 2: Saturation regime............................................................................... 44
3.III.a High resistivity structure ................................................................................. 46
3.III.b Low resistivity structure .................................................................................. 49
3.IV Region 3: Negative differential resistivity regime............................................ 53
3.V Region 4: High current regime .......................................................................... 56
3.VI Non-isothermal conditions ................................................................................ 58
3.VII Conclusions.......................................................................................................... 62
3. VIII References ............................................................................................................ 63
Chapter 4 High Injection Mechanisms in P+-N--N+ Substrate
Diodes: Theory Validation................................................................... 65
4.I Introduction ......................................................................................................... 66
4.II Analysis of P+-N--N+ structures........................................................................ 67
4.II.a Low injection conditions.................................................................................. 68
4.II.b High injection conditions................................................................................. 68
4.II.c Auger recombination....................................................................................... 79
4.III Simulations vs. measurements under high injection conditions ................... 81
4.III.a Carriers concentration ..................................................................................... 82
4.III.b Electric field and potential .............................................................................. 83
4.III.c Recombination currents................................................................................... 85
4.III.d Simulated IA(VA) characteristic...................................................................... 86
4.III.e Experimental verifications .............................................................................. 86
4.IV Conclusions..........................................................................................................87
4.V References ............................................................................................................ 87
Chapter 5 P+-N--N+ Substrate Diodes under Ultra High
Injection Conditions .............................................................................. 89
5.I Introduction ......................................................................................................... 90
5.II Simulations vs. measurements under ultra high injection conditions .......... 91
5.II.a Measured and simulated IA(VA) .................................................................... 91
5.II.b Carriers concentration ..................................................................................... 92
5.II.c Electric field ................................................................................................... 95
5.II.d Potential......................................................................................................... 97
5.II.e Recombination currents................................................................................... 98
5.II.f Ultra high injection conditions....................................................................... 100
5.II.g Modeling issues............................................................................................. 103
5.III TLP Characterization........................................................................................ 104
5.IV Process and layout variations........................................................................... 108
5.IV.a Base region length effects................................................................................ 108
5.IV.b Base region doping effects............................................................................... 108
5.IV.c Lifetime effects.............................................................................................. 109
5.IV.d End regions doping effects.............................................................................. 110
5.IV.e End regions length ........................................................................................ 111
5.IV.f Carrier-carrier scattering effects...................................................................... 112
5.V Conclusions........................................................................................................ 112
5.VI References .......................................................................................................... 114
Chapter 6 LDMOS Transistors under High Current Conditions ............... 115
6.I Introduction ....................................................................................................... 116
6.II Experimental results.......................................................................................... 118
6.II.a Poly length variation effects............................................................................ 119
6.II.b CO-PS spacing variation effects .................................................................... 120
6.II.c W variation effects........................................................................................ 120
6.III Simulation results ..............................................................................................121
6.III.a Simulation approach..................................................................................... 121
6.III.b Drift region length ........................................................................................ 123
6.III.c Another point of view: the Kirk effect ............................................................ 125
6.III.d DIBL effect.................................................................................................. 129
6.III.e Breakdown behavior of LDMOSt................................................................ 130
6.III.f Application of a gate voltage ......................................................................... 135
6.III.g CO-PS distance ........................................................................................... 136
6.III.h Temperature effects and failure analysis ......................................................... 137
6.IV Conclusions........................................................................................................139
6.V References ..........................................................................................................140
Chapter 7 Transient Phenomena in ggnMOSt’s under
TLP Conditions..................................................................................... 143
7.I Introduction ....................................................................................................... 144
7.II Simulated devices .............................................................................................. 145
7.III Results and discussion: LDD option.............................................................. 147
7.IV Results and discussion: non-LDD implant.................................................... 152
7.V Overlap capacitance evaluation ....................................................................... 154
7.VI VMAX versus VT1.................................................................................................. 158
7.VII Soft failures.........................................................................................................160
7.VIII Latency aspects .................................................................................................. 162
7.IX Conclusions........................................................................................................ 163
7.X References .......................................................................................................... 164
Chapter 8 Conclusions ............................................................................................ 167
8.I Summary ............................................................................................................. 168
8.II Conclusions........................................................................................................169
8.III Recommendations for future research ........................................................... 171

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Gianluca Boselli 2001 dessis.

halomen

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soulhenry

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wufuwei

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leiyuming

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xuleiwx

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leiya21

回复 1# duduxy


    很好的资料！