我的CCS#信号，ADS#信号，BLAST＃，LW/R#信号严格按照PCI 9054 Data Book V2.1中的page5-36中的"Timing Diagram 5-13. Local Bus Write to Configuration Register"设置。另外寄存器DMCFGA设置为0x“80000000”，允许LOCAL BUS READ TO CONFIGURATION REGISTER的访问。
Configure Register: How to reconfigure 9xxx internal register from local CPU?
Answer：
Very similar to Direct Master Write action.
The differences are;
- A signal called CCS# is asserted (by local CPU) during address phase (i.e. assert/deassert at the same time ADS# does, in C/J mode).
- READY# signal is already enabled and asserted/deasserted by PCI9xxx.
- The cycle should be single cycle, and the bus width should be 32bit.
- For address, only lower 16 bits are decoded and upper 16bits are "Don't care".
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2006-9-20 14:24:43
楼主