上海张江Atheros招聘IC DV数字验证工程师

crow016

[原创] 上海张江招聘IC DV数字验证工程师

1，[dv]数字验证工程师 1）精通芯片验证方法学。 2）精通vera/verilog/system verilog。 3）精通verification flow/test bentch。 4）2-3年工作经验。 5）有相关IC工作经验者优先考虑。 公司地址：浦东张江高科，离地铁站步行5分钟以内。待遇从优，合则约见。 联系方式：abenhuang016@126.com

crow016

JD 详情:

QUALIFICATION (DETAIL):
Education:
MS, Preferred Major: Electrical Engineering or related discipline
Experience:
-Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design verification skills
-Experience in using event-driven simulators like VCS
-Fluent in Verilog for design verification
-Experience in writing testbench using System Verilog/Vera/Specman
-Knowledge of peripheral IP intergration (PCI-E, PCI)
-Knowledge of DMA/ AMBA/AHB
-Experience with one or more scripting languages: Perl, TCL, Shell
-Superior debugging skills for large ASIC designs
-Strong written and verbal communication skills
DESCRIPTION OF FUNCTION & RESPONSIBILITY:

-Working within an ASIC DV team to develop reusable block-level and ASIC testbenches using high-level verification language (System Verilog and VMM).
-Develop new ASIC verification environments to support ASIC development.
-Review RTL architectural and implementation specifications.
-Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC ASICs.
-Define and implement code/functional coverage plans.
-Develop testing and regression methodologies for new verification flow.
-Incorporate reusability into all aspects of the verification environment.
-Develop/maintain/enhance environment tools/scripts/makefiles.

Abenhuang016@126.com

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