someone can upload CadenceLow-PowerMethodologyKit8.2.0

vanduongbk · 发表于 2010-6-4 12:43:27

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someone can upload CadenceLow-PowerMethodologyKit8.2.0The Cadence Low-Power Methodology Kit 8.2.0 is an update release of the Cadence Low-Power
Methodology Kit 8.1.0. This Kit includes updates to following modules and tool versions as below:

1  Kit Content Overview
2  Digital Low Power Methodology
3  Library Qualification
4  SRD Overview
5  Low Power RTL Design
6  MSV and DVFS
7  PSO
8  CPF Creation, Authoring and Refining: Update
9  Low Power Synthesis: Update
10  Power Aware Design for Test: Update
11  Conformal Low Power: Update
12  Low-Power Functional and Formal Verification: Update
13  LP ECO Methodology: Update
14  Floorplanning for LP design and I/O ring Development: Update
15  Power planning: Update
16  LP timing and SI Closure: Update
17  PV: Update
18  Power Sign Off: Update
19  VoltageStorm View generation: Update
20  QRC techfile generation: Update
21  ECSM generation: Update
22  CDB view generation: Update
23  CapTable Generation: Update
24  Design Reuse: Update

Key Feature Updates

1.  Tool BoM update for all the tools used (please refer to README for Tool Versions)
2.  Work around were reduced as tools CCRs got fixed
3.  CPF1.0e, Hierarchal CPF
4.  Integrater for CPF merging
5.  Physical Synthesis
6.  Power Exploration based on build power model
7.  Foundation Flow for PnR
8.  CPF based timing and SI flow for top level
9.  ELC for ECSM generation (SLC last time)
10. Multithreading for SoCE
11. Verilog/SV based new verification environment for Verification
12.  IEM for the low power mode and transition coverage
13. Flow improvement in Scan and Mbist