VHDL程序24小时

Kwon

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity digital_clock is

port(

reset,clk: in std_logic;

hour,minitue,second: out std_logic_vector(7 downto 0);

hex0,hex1,hex2,hex3,hex4,hex5: out std_logic_vector(6 downto 0));

end digital_clock;

architecture one of digital_clock is

signal clk_count: std_logic_vector(22 downto 0);

signal clkm: std_logic;

signal second1,second2: std_logic_vector(3 downto 0);

signal minitue1,minitue2: std_logic_vector(3 downto 0);

signal hour1,hour2: std_logic_vector(3 downto 0);

begin

hour(7 downto 0) <= hour2(3 downto 0) & hour1 (3 downto 0);

minitue(7 downto 0) <= minitue2(3 downto 0) & minitue1(3 downto 0);

second(7 downto 0) <= second2(3 downto 0) & second1(3 downto 0);

process(clk)

begin

if (clk'event and clk ='1') then

clk_count <= clk_count + 1;

end if;

end process;

clkm <= clk_count(22);

------------------------

process(clkm)

begin

if(reset='1')then

hour2 <= "0000";hour1<="0000";minitue2 <="0000"; minitue1 <="0000"; second2<="0000"; second1<="0000";

elsif (clkm'event and clkm='1') then

if (hour2 = "0101" and hour1 ="1001" and minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then

hour2 <= "0000"; hour1 <= "0000"; minitue2 <="0000"; minitue1 <="0000"; second2<="0000"; second1<="0000";

elsif(hour1 ="1001" and minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then

hour2 <= hour2 +1;hour1 <= "0000";minitue2 <="0000";minitue1 <="0000";second2<="0000";second1<="0000";

elsif(minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then

hour1 <= hour1 +1;minitue2 <="0000";minitue1 <="0000";second2<="0000";second1<="0000";

elsif(minitue1 ="1001" and second2 ="0101" and second1 ="1001")then

minitue2 <=minitue2 +1;minitue1 <="0000";second2<="0000";second1<="0000";

elsif(second2 ="0101" and second1 ="1001")then

minitue1 <=minitue1 +1;second2<="0000";second1<="0000";

elsif(second1 ="1001")then

second2 <= second2 +1;second1 <= "0000";

else

second1 <= second1 +1;

end if;

end if;

end process;

------------------------

process(hour2,hour1,minitue2,minitue1,second2,second1)

begin

case second1(3 downto 0) is

when "0000" => hex0(6 downto 0) <="1000000";

when "0001" => hex0(6 downto 0) <="1111001";

when "0010" => hex0(6 downto 0) <="0100100";

when "0011" => hex0(6 downto 0) <="0110000";

when "0100" => hex0(6 downto 0) <="0011001";

when "0101" => hex0(6 downto 0) <="0010010";

when "0110" => hex0(6 downto 0) <="0000010";

when "0111" => hex0(6 downto 0) <="1111000";

when "1000" => hex0(6 downto 0) <="0000000";

when "1001" => hex0(6 downto 0) <="0010000";

when others => hex0(6 downto 0) <="1000000";

end case;

case second2(3 downto 0) is

when "0000" => hex1(6 downto 0) <="1000000";

when "0001" => hex1(6 downto 0) <="1111001";

when "0010" => hex1(6 downto 0) <="0100100";

when "0011" => hex1(6 downto 0) <="0110000";

when "0100" => hex1(6 downto 0) <="0011001";

when "0101" => hex1(6 downto 0) <="0010010";

when others => hex1(6 downto 0) <="1000000";

end case;

case minitue1(3 downto 0) is

when "0000" => hex2(6 downto 0) <="1000000";

when "0001" => hex2(6 downto 0) <="1111001";

when "0010" => hex2(6 downto 0) <="0100100";

when "0011" => hex2(6 downto 0) <="0110000";

when "0100" => hex2(6 downto 0) <="0011001";

when "0101" => hex2(6 downto 0) <="0010010";

when "0110" => hex2(6 downto 0) <="0000010";

when "0111" => hex2(6 downto 0) <="1111000";

when "1000" => hex2(6 downto 0) <="0000000";

when "1001" => hex2(6 downto 0) <="0010000";

when others => hex2(6 downto 0) <="1000000";

end case;

case minitue2(3 downto 0) is

when "0000" => hex3(6 downto 0) <="1000000";

when "0001" => hex3(6 downto 0) <="1111001";

when "0010" => hex3(6 downto 0) <="0100100";

when "0011" => hex3(6 downto 0) <="0110000";

when "0100" => hex3(6 downto 0) <="0011001";

when "0101" => hex3(6 downto 0) <="0010010";

when others => hex3(6 downto 0) <="1000000";

end case;

case hour1(3 downto 0) is

when "0000" => hex4(6 downto 0) <="1000000";

when "0001" => hex4(6 downto 0) <="1111001";

when "0010" => hex4(6 downto 0) <="0100100";

when "0011" => hex4(6 downto 0) <="0110000";

when "0100" => hex4(6 downto 0) <="0011001";

when "0101" => hex4(6 downto 0) <="0010010";

when "0110" => hex4(6 downto 0) <="0000010";

when "0111" => hex4(6 downto 0) <="1111000";

when "1000" => hex4(6 downto 0) <="0000000";

when "1001" => hex4(6 downto 0) <="0010000";

when others => hex4(6 downto 0) <="1000000";

end case;

case hour2(3 downto 0) is

when "0000" => hex5(6 downto 0) <="1000000";

when "0001" => hex5(6 downto 0) <="1111001";

when "0010" => hex5(6 downto 0) <="0100100";

when "0011" => hex5(6 downto 0) <="0110000";

when "0100" => hex5(6 downto 0) <="0011001";

when "0101" => hex5(6 downto 0) <="0010010";

when others => hex5(6 downto 0) <="1000000";

end case;

end process;

end one;

－－－－－在DE2板上验证
时钟频率有点高，可以在clk_count中增加位数作调整

xiongherui

了解一下

hxl888

不 know~非常不know