makefile 不认include 的verilog

sunnyzhu

请问一下,在用makefile做仿真时，因为有很多的verilog code需要都include进来，可怎么都不认，总是出现以下问题：
Error-[SFC0R] Source file cannot be opened
  Source file "`include" connot be opened for reading due to"No such file or directory".

这是什么原因造成的，我是新手，请教大家。
我把我的file.v写一部份出来：
`include "/data/project/aa/a.v"
`include "/data/project/bb/b.v"
就是类似这样，不知道为何总是出错，之前用nc跑就没有问题。

kevin20899

Thanks a lot !!!!!!!!!

xxl2

是反斜杠的问题吗

kinglin

最有可能是路径不对！可以采用绝对路径！

neptune1983

既然想用makefile，可以直接采用filelist文件来指定文件路径的

jemmyplus

在/data之前加一個.
這樣的意思是告訴verilog simulator去你目前目錄下的data目錄去找你的verilog code

`include "./data/project/aa/a.v"
`include "./data/project/bb/b.v"

hyperpicc

I think 'make' is not responsible for the file path. It is related to your simulator actually. First of all, you have to know where you are when the makefile executes the simulator. Some suggest that you may define your "project root directory" in your makefile like:

PROJ_ROOT=/home/user_name/proejcts/proj_1

and then you should based on the variable ${PROJ_ROOT}. I think it may easier when you encounter the troubles like this.

longyv424

makefile和include的没有什么关系吧
要么文件在filelist里面指定位置，要么在跑的时候用命令行指定一个路径吧

tomzhuo

学习一下

suntou

kankan