library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk : in STD_LOGIC;
rst_n : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
divout : out STD_LOGIC);
end top;
architecture Behavioral of top is
signal cnt: std_logic_vector(7 downto 0);
signal div: std_logic;
signal clkbuf: std_logic;
begin
divout<=div;
clkbuf<=not clk;
process(rst_n,clk,sw)
begin
if rst_n='0' then
cnt<=(others=>'0');
div<='0';
elsif sw="00000000" then
div<=clkbuf;
elsif clk'event and clk='1' then
if cnt=sw-1 then
div<=not div;
cnt<=(others=>'0');
else
cnt<=cnt+1;
end if;
end if;
end process;