LOW POWER ASYNCHRONOUS DIGITAL SIGNAL PROCESSING

kevinwjs

Chapter 1: Introduction ....................................................................................14
Digital Signal Processing ...............................................................................15
Evolution of digital signal processors ....................................................17
Architectural features of modern DSPs .........................................................19
High performance multiplier circuits .....................................................20
Memory architecture ..............................................................................21
Data address generation .........................................................................21
Loop management ..................................................................................23
Numerical precision, overflows and rounding .......................................24
Architecture of the GSM Mobile Phone System ...........................................25
Channel equalization ..............................................................................28
Error correction and Viterbi decoding ...................................................29
Speech transcoding ................................................................................31
Half-rate and enhanced full-rate coding .............................................33
Summary of processing for GSM baseband functions ...........................34
Evolution towards 3rd generation systems ............................................35
Digital signal processing in 3G systems ........................................................36
Structure of thesis ..........................................................................................37
Research contribution ....................................................................................37
Chapter 2: Design for low power ......................................................................39
Sources of power consumption ......................................................................39
Dynamic power dissipation ....................................................................39
Leakage power dissipation .....................................................................40
Power reduction techniques ...........................................................................41
Reducing the supply voltage ..................................................................41
Architecture-driven voltage scaling ...................................................43
Adaptive supply voltage scaling ........................................................45
Reducing the voltage swing ...............................................................45
Adiabatic switching ............................................................................46
Reducing switched capacitance .............................................................47
Feature size scaling ............................................................................49
Transistor sizing .................................................................................50
Layout optimization ...........................................................................51
SOI CMOS technology ......................................................................51
Reducing switching activity ...................................................................52
Reducing unwanted activity ...............................................................53
Choice of number representation and signal encoding ......................54
Evaluation of number representations for DSP arithmetic .................58
Algorithmic transformations ..............................................................63
Reducing memory traffic ...................................................................63
Asynchronous design .....................................................................................65
Asynchronous circuit styles ...................................................................66
Delay insensitive design .....................................................................66
Bundled-data design ...........................................................................703
Asynchronous handshake circuits ......................................................71
Latch controllers for low power asynchronous circuits .........................73
Advantages of asynchronous design ......................................................78
Elimination of clock distribution network .........................................78
Automatic idle-mode ..........................................................................79
Average case computation .................................................................80
Reduced electromagnetic interference ...............................................80
Modularity of design ..........................................................................81
Disadvantages compared to clocked designs .........................................82
Lack of tool support ...........................................................................82
Reduced testability .............................................................................82
Chapter 3: CADRE: A new DSP architecture ................................................84
Specifications .................................................................................................84
Sources of power consumption ......................................................................84
Processor structure .........................................................................................85
Choice of parallel architecture ...............................................................86
FIR Filter algorithm ...........................................................................86
Fast Fourier Transform .......................................................................89
Choice of number representation .......................................................90
Supplying instructions to the functional units ........................................90
Supplying data to the functional units ....................................................92
Instruction buffering ..............................................................................95
Instruction encoding and execution control ...................................................96
Interrupt support ...................................................................................101
DSP pipeline structure .........................................................................102
Summary of design techniques ....................................................................104
Chapter 4: Design flow ....................................................................................106
Design style .................................................................................................106
High-level behavioural modelling ...............................................................106
Modelling environment ........................................................................106
Datapath model design .........................................................................108
Control model design ...........................................................................108
Combined model design .......................................................................111
Integration of simulation and design environment ..............................114
Circuit design ...............................................................................................114
Assembler design .........................................................................................114
Chapter 5: Instruction fetch and the instruction buffer ...............................118
Instruction fetch unit ....................................................................................118
Controller operation .............................................................................119
PC incrementer design .........................................................................120
Instruction buffer design ..............................................................................123
Word-slice FIFO structure ...................................................................125
Looping FIFO design ...........................................................................127
Write and read token passing ...........................................................128
Overall system design ..........................................................................130
PC latch scheme ...................................................................................131
Control datapath design .......................................................................1324
Evaluation of design .............................................................................133
Results ..................................................................................................134
Loop counter performance ...............................................................134
Chapter 6: Instruction decode and index register substitution ...................137
Instruction decoding ....................................................................................137
First level decoding ..............................................................................138
Parallel instructions ..........................................................................139
Move-multiple-immediate instructions ............................................140
Other instructions .............................................................................141
Changes of control flow ...................................................................141
Second level decoding .........................................................................142
Third level decoding ............................................................................143
Fourth level decoding ...........................................................................143
Control / setup instruction execution ...........................................................144
Branch unit ...........................................................................................144
DO Setup unit .......................................................................................144
Index interface ......................................................................................145
LS setup unit ........................................................................................145
Configuration unit ................................................................................145
The index registers .......................................................................................145
Index register arithmetic ......................................................................146
Circular buffering .............................................................................146
Bit-reversed addressing ....................................................................147
Index unit design ..................................................................................147
Index register substitution in parallel instructions .......................................149
Chapter 7: Load / store operation and the register banks ...........................151
Load and store operations ............................................................................152
Decoupled load / store operation .........................................................152
Read-before-write ordering ..................................................................152
Write-before-read ordering ..................................................................153
Load / store pipeline operation ....................................................................154
Address generation unit .......................................................................156
Address ALU design ........................................................................158
Lock interface ......................................................................................161
Register bank design ....................................................................................162
Data access patterns .............................................................................165
FIR filter data access patterns ..........................................................165
Autocorrelation data access patterns ................................................165
Register bank structure .........................................................................166
Write organization ................................................................................168
Read organisation .................................................................................170
Read operation ..................................................................................171
Register locking ...................................................................................173
Chapter 8: Functional unit design ..................................................................175
Generic functional unit specification ...........................................................176
Decode stage interfaces ........................................................................176
Index substitution stage interfaces .......................................................1765
Secondary interfaces ........................................................................179
Register read stage ...............................................................................179
Execution stage ....................................................................................179
Functional unit implementation ...................................................................180
Arithmetic / logical unit implementation .....................................................182
Arithmetic / logic datapath design .......................................................184
Multiplier Design .............................................................................185
Input Multiplexer and Rounding Unit ..............................................189
Adder Design ....................................................................................190
Logic unit design ..............................................................................192
Chapter 9: Testing and evaluation .................................................................194
Functional testing ........................................................................................194
Power and performance testing ...................................................................196
Recorded statistics ................................................................................196
Operating speed and functional unit occupancy ..............................197
Memory and register accesses ..........................................................197
Instruction issue ................................................................................197
Address register and index register updating ...................................197
Register read and write times ...........................................................198
Results .........................................................................................................198
Instruction execution performance .......................................................198
Power consumption results ..................................................................199
Evaluation of architectural features .....................................................202
Register bank performance ...............................................................202
Use of indexed accesses to the register bank ...................................206
Effect of instruction buffering ..........................................................207
Effect of sign-magnitude number representation .............................208
Comparison with other DSPs ......................................................................209
Detailed comparisons ...........................................................................209
Other comparisons ...............................................................................212
OAK / TEAK DSP cores ..................................................................213
Texas Instruments TMS320C55x DSP ............................................213
Cogency ST-DSP .............................................................................213
Non-commercial architectures .........................................................213
Evaluation ....................................................................................................214
Chapter 10: Conclusions ..................................................................................217
CADRE as a low-power DSP ......................................................................217
Improving CADRE ......................................................................................218
Scaling to smaller process technologies ...............................................218
Optimising the functional units ............................................................220
Multiplier optimisation .....................................................................220
Pipelined multiply operation ............................................................221
Adder optimisation ...........................................................................221
Improving overall functional unit efficiency ...................................222
Optimising communication pathways ..................................................222
Optimising configuration memories ....................................................222
Changes to the register bank ................................................................223
Conclusions .................................................................................................2246
References ........................................................................................................225
Appendix A: The GSM full-rate codec.............................................................241
Speech pre-processing ................................................................................. 241
LPC Analysis............................................................................................... 242
Short-term analysis filtering ........................................................................ 243
Long-term prediction analysis ..................................................................... 244
Regular pulse excitation encoding............................................................... 246
Appendix B: Instruction set ..............................................................................248
Appendix C: The index register units ..............................................................253
Index unit structure...................................................................................... 253
Index ALU operation................................................................................... 255
Split adder / comparator design ........................................................... 257
Verification of index ALU operation................................................... 259
Appendix D: Stored opcode and operand configuration................................260
Functional unit opcode configuration.......................................................... 260
Arithmetic operations........................................................................... 262
Logical operations................................................................................ 264
Conditional execution .......................................................................... 265
Stored operand format ................................................................................. 266
Index update encoding................................................................................. 267
Load / store operation.................................................................................. 267

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