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in our vmm testbench, an axi master bfm is needed to write and read the pcie core and some internal registers. and our axi slave just suppport INCR AXI burst type,all burst length data transfer and support 1,2,4,8 burst size data transfer .Could I use the command based model of axi vip: axi_master_vmt to build such axi master bfm?
the reg write task can be written like below?
Class axi_master_bfm extends vmm_xactor;
axi_master_vmt axi_master;
.....
.....
task automatic reg_write( bit [63:0] addr, logic [31:0] data[],int len, int size );
integer nWriteBufferHandle,nWriteBufferHandle1;
integer nCmdHandle;
$display("%t prepare to read %8h",$time,addr);
axi_master.new_buffer(nBufferHandle);
axi_master.copy_buffer(nBufferHandle, nWriteBufferHandle1);
axi_master.set_buffer_attr_bitvec(nWriteBufferHandle1, `DW_VIP_AXI_ADDR, 0, addr);
axi_master.set_buffer_attr_bitvec(nWriteBufferHandle1, `DW_VIP_AXI_ALEN, 0, len);
axi_master.set_buffer_attr_bitvec(nWriteBufferHandle1, `DW_VIP_AXI_ASIZE, 0, size);
axi_master.set_buffer_attr_bitvec(nWriteBufferHandle2, `DW_VIP_AXI_ABURST, 0, 2'b01);
axi_master.set_buffer_attr_int(nWriteBufferHandle1, `DW_VIP_AXI_WRITE, 0, `VMT_TRUE);
for(int i=0; i<len;i++)
axi_master.set_buffer_attr_bitvec(nWriteBufferHandle1, `DW_VIP_AXI_DATA, i, data[i]);
axi_master.send_xact(`VMT_DEFAULT_STREAM_ID, nWriteBufferHandle1, nCmdHandle);
endtask
.....
......
endclass
could you give some good advice how to write this type of axi master bfm? thank you very much! |
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发表于 2010-4-12 09:08:56
