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在做LVS的时候，pip电容版图提取不了，这是为什么呢？单独只画一个电容，做lvs，会显示说nothing in layout。
lvs report如下 OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
Error: Components with non-identical signal pins.
Error: Different numbers of instances.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT CHAOSGEN_LAYOUT1 CHAOSGEN_LAYOUT1
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
LVS COMPONENT TYPE PROPERTY element
LVS COMPONENT SUBTYPE PROPERTY model
LVS PIN NAME PROPERTY phy_pin
LVS POWER NAME "VCC" "vcc" "vcc!" "VDD" "vdd" "vdd!" "DVDD"
LVS GROUND NAME "GND" "gnd" "gnd!" "VSS" "vss" "vss!" "DVSS"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 200
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION RC LAYOUT
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR NO
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES NO
LVS REDUCE C(pip) PARALLEL [ TOLERANCE c_length 0 c_width 0 ]
LVS REDUCE MN PARALLEL [ TOLERANCE l 1 ]
LVS REDUCE MP PARALLEL [ TOLERANCE l 1 ]
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY r r r 1
TRACE PROPERTY mn w w 1
TRACE PROPERTY mn l l 1
TRACE PROPERTY mp w w 1
TRACE PROPERTY mp l l 1
TRACE PROPERTY d(pn_5p0) a a 1
TRACE PROPERTY d(pn_3p3) a a 1
TRACE PROPERTY d(np_5p0) a a 1
TRACE PROPERTY d(np_3p3) a a 1
TRACE PROPERTY d(nwp) a a 1
TRACE PROPERTY d(dnwp) a a 1
TRACE PROPERTY d(np_5p0_esd) a a 1
TRACE PROPERTY d(np_3p3_esd) a a 1
TRACE PROPERTY c(pip) c_length c_length 1
TRACE PROPERTY c(pip) c_width c_width 1
TRACE PROPERTY c(pip) m m 1
**************************************************************************************************************
COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS
**************************************************************************************************************
(Cells with the same ( or corresponding ) name that have different signal
pin names are listed below. Pins that do not appear in all corresponding
cells in both source and layout are ignored by the comparison algorithm.)
Layout Component Type: R (3 pins): (p n) sub
Layout Extra Pins: sub
Source Component Type: R (2 pins): (p n)
No Extra Pins.
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
Error: Different numbers of instances (see below).
LAYOUT CELL NAME: CHAOSGEN_LAYOUT1
SOURCE CELL NAME: CHAOSGEN_LAYOUT1
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 4 4
Nets: 38 38
Instances: 63 31 * MN (4 pins)
44 23 * MP (4 pins)
0 1 * C (2 pins)
4 4 R (2 pins)
------ ------
Total Inst: 111 59
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 4 4
Nets: 27 27
Instances: 21 21 MN (4 pins)
13 13 MP (4 pins)
0 1 * C (2 pins)
1 1 R (2 pins)
2 2 _nor2v (5 pins)
1 1 _smn2b (5 pins)
2 2 _smn2v (4 pins)
3 3 _sup2v (4 pins)
------ ------
Total Inst: 43 44
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
SOURCE ERRORS
DISC#
**************************************************************************************************************
Properties Missing on Instances:
1 property c_width not found on CC0 (C)
2 property c_length not found on CC0 (C)
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
3 ** missing instance ** CC0 C(PIP)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 4 4 0 0
Nets: 27 27 0 0
Instances: 21 21 0 0 MN(NMOS_3P3)
13 13 0 0 MP(PMOS_3P3)
0 0 0 1 C(PIP)
1 1 0 0 R(NPLUS_U)
2 2 0 0 _nor2v
1 1 0 0 _smn2b
2 2 0 0 _smn2v
3 3 0 0 _sup2v
------- ------- --------- ---------
Total Inst: 43 43 0 1
o Statistics:
2 source properties were missing.
79 layout mos transistors were reduced to 26.
53 mos transistors were deleted by parallel reduction.
4 series layout resistors were reduced to 1. 3 connecting nets were deleted.
4 series source resistors were reduced to 1. 3 connecting nets were deleted.
o Initial Correspondence Points:
Ports: VDD VSS CHAOS_BIN CLK
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec |
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发表于 2015-8-12 09:52:29
