请教calibre问题

zhj1214 · 发表于 2010-3-23 11:26:58

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初学calibre,有很多不明白的地方，望指导下，谢谢！下面是我的一个report的一部分
o Statistics:
8 source properties were missing.

               CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Connectivity errors.
  Error: Instances of different types or subtypes were matched.
  Warning:  Ambiguity points were found and resolved arbitrarily.
layout CELL NAME:       CE5000_Analog2
SOURCE CELL NAME:       analog_sch
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
            Layout Source       Component Type
            ------ ------       --------------
Ports:             8       8
Nets:          472    235 *
Instances:       416    291 * MN (4 pins)
               432    303 * MP (4 pins)
                  20       3 * Q (3 pins)
                  93       11 * C (2 pins)
               366       42 * R (2 pins)
            ------ ------
Total Inst:    1327    650

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
            Layout Source       Component Type
            ------ ------       --------------
Ports:             8       8
Nets:          160    160
Instances:       59       59       MN (4 pins)
                  48       48       MP (4 pins)
                  3       3       Q (3 pins)
                  10       10       C (2 pins)
                  32       32       R (2 pins)
                  45       45       INV (2 pins)
                  5       5       NAND2 (3 pins)
                  1       1       NAND3 (4 pins)
                  5       5       NOR2 (3 pins)
                  1       1       AOI_2_1 (4 pins)
                  11       11       SDW2 (3 pins)
                  1       1       SDW3 (4 pins)
                  9       9       SMN2 (4 pins)
                  33       33       SMP2 (4 pins)
            ------ ------
Total Inst:    263    263

   * = Number of objects in layout different from number in source.

**************************************************************************************************************
                              INCORRECT OBJECTS
**************************************************************************************************************

LEGEND:
-------
  ne  = Naming Error (same layout name found in source
      circuit, but object was matched otherwise).

**************************************************************************************************************
                                 INCORRECT NETS
DISC#  LAYOUT NAME                                        ne  SOURCE NAME
**************************************************************************************************************
  1 Net VDD                                                 VDD
   --------------------------                               --------------------------
   --- Incorrect Devices On This Net ---
   C730(314.660,553.440)  C(CN)                            ** no similar instance **
      pos: GND                                                 ** GND **
      neg: VDD                                                 ** VDD **
   R612(400.200,435.210)  R(RH)                            XI0/RR443  R(RP)
      pos: 82                                                 pos: XI0/net997
      neg: VDD                                                 neg: VDD

R590(325.910,217.320)  R(RH)                            XI0/RR494  R(RP)
      pos: VDD                                                 pos: VDD
      neg: 78                                                 neg: XI0/P645_G
   R550(322.920,309.710)  R(RH)                            XI0/RR491  R(RP)
      pos: 80                                                 neg: XI0/DATAout
      neg: VDD                                                 pos: VDD
   R377(332.920,164.650)  R(RO)                            XI0/RR537  R(RP)
      pos: VDD                                                 neg: VDD
      neg: 79                                                 pos: XI0/R537_PLUS

  --- Correct Devices On This Net ---
   (cell ports)                                           (cell ports)
      vdd: VDD                                                 vdd: VDD
      GND: GND                                                 GND: GND
      AVDD: AVDD                                              AVDD: AVDD
      OUT: OUT                                                 OUT: OUT
      RST: RST                                                 RST: RST
      EP: EP                                                 EP: EP
      CLK_OUT2: CLK_OUT2                                     CLK_OUT2: CLK_OUT2
      CLK_OUT1: CLK_OUT1                                     CLK_OUT1: CLK_OUT1
   (NAND3)                                                 (NAND3)
      output: 68                                              output: XI0/net524
      input: CLK_OUT2                                        input: CLK_OUT2
      input: 71                                              input: XI0/DataClk
      input: VDD                                              input: VDD

************************************************************************************************************
                              INCORRECT INSTANCES
DISC#  LAYOUT NAME                                        ne  SOURCE NAME
**************************************************************************************************************
  3 R276(123.130,46.030)  R(RO)                            XI0/RR361  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  4 R303(212.440,323.640)  R(RO)                            XI0/RR413  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  5 R330(185.550,424.390)  R(RO)                            XI0/RR386  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  6 R331(185.550,427.270)  R(RO)                            XI0/RR388  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  7 R353(332.920,92.650)  R(RO)                            XI0/RR550  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  8 R360(332.920,113.650)  R(RO)                            XI0/RR542  R(RP)
      bad component subtype
--------------------------------------------------------------------------------------------------------------
  9 R369(332.920,140.650)  R(RO)                            XI0/RR539  R(RP)
      bad component subtype
我拿LOGLVS做的是没问题，到calibre就出现很多问题，请教下各位大大们？谢谢！

sjingf · 发表于 2010-3-23 21:34:42

问题就在于电阻的类型不匹配,版图上提取出来的是RH和RO,但网表中对应的却是RP.仔细看看dracula和calibre的rule file ,dracula应该没有检查电阻类型,而calibre检查了.在calibre 的rule file中有定义器件类型的.确认好版图中电阻类型和网表中电阻类型.另外,怎么没有比较尺寸呢?

zhj1214 · 发表于 2010-3-24 10:16:06

谢谢！这个report不全，以前用别的做LVS，都没太注意类型匹配。thinks！！

89700307 · 发表于 2010-3-25 15:23:31

电阻类型问题，可以修改CDL文件里的电阻名，对应地改成RO

zhj1214 · 发表于 2010-3-25 15:58:15

嗯这个改好了谢谢！

dennischen06 · 发表于 2010-5-19 11:19:01

thanks

dilyyao · 发表于 2010-6-24 21:15:56

学习了

raga21 · 发表于 2017-5-30 21:33:33

IS the GDS and pg.v file is same???

[求助] 请教calibre问题

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