用libero综合出现警告

liu_jing_yang

为什么这个程序综合通不过？开发软件为libero，朋友们给分析分析怎么回事？有用libero vhdl语言编写程序的请加好友QQ155337199，相互交流学习经验。源程序： library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity wr is
port( mcudata: in std_logic_vector(7 downto 0);
mcuaddress: in std_logic_vector(11 downto 0);
clock : in std_logic;
wr : in std_logic;
cs : in std_logic;
dataout : out std_logic_vector(7 downto 0));
end;
architecture wrbus of wr is
signal addresstemp: std_logic_vector(11 downto 0);
signal flag: std_logic_vector(1 downto 0);
signal datatemp1,datatemp2,datatemp3,datatemp4 : std_logic_vector(7 downto 0);
begin
addresstemp(11 downto 0)<= mcuaddress(11 downto 0); process(clock) begin
if clock'event and clock = '0' then
if addresstemp = "000000000000" then flag <= "00";
elsif addresstemp = "000000000001" then flag <= "01";
elsif addresstemp = "000000000010" then flag <= "10";
elsif addresstemp = "000000000011" then flag <= "11";
end if;
end if;
end process;
process(wr)
begin
if wr'event and wr = '0' then
if ((cs = '0') and (flag ="00")) then
datatemp1 <= mcudata;
elsif ((cs = '0') and (flag ="01")) then
datatemp2 <= mcudata;
elsif ((cs = '0') and (flag ="10")) then
datatemp3 <= mcudata;
elsif ((cs = '0') and (flag ="11")) then
datatemp4 <= mcudata;
end if;
end if;
end process;
dataout <= mcudata; end;
综合错误提示： @W: CL169 :"C:\Actelprj\wr\hdl\wr.vhd":40:0:40:1|Pruning Register datatemp4(7 downto 0) @W: CL169 :"C:\Actelprj\wr\hdl\wr.vhd":40:0:40:1|Pruning Register datatemp3(7 downto 0) @W: CL169 :"C:\Actelprj\wr\hdl\wr.vhd":40:0:40:1|Pruning Register datatemp2(7 downto 0) @W: CL169 :"C:\Actelprj\wr\hdl\wr.vhd":40:0:40:1|Pruning Register datatemp1(7 downto 0) @W: CL169 :"C:\Actelprj\wr\hdl\wr.vhd":25:0:25:1|Pruning Register flag(1 downto 0) @W: CL159 :"C:\Actelprj\wr\hdl\wr.vhd":10:0:10:9|Input mcuaddress is unused @W: CL159 :"C:\Actelprj\wr\hdl\wr.vhd":11:0:11:4|Input clock is unused @W: CL159 :"C:\Actelprj\wr\hdl\wr.vhd":12:0:12:1|Input wr is unused @W: CL159 :"C:\Actelprj\wr\hdl\wr.vhd":13:0:13:1|Input cs is unused @W: BN246 |Failed to find top level module 'work.wr' as specified in project file

liu_jing_yang

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