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A 10-Bit 500-MSps 55-mW CMOS ADC
Abstract—A pipelined ADC incorporates a digital foreground
calibration technique that corrects errors due to capacitor mismatch,
gain error, and op amp nonlinearity. Employing a highspeed,
low-power op amp topology and an accurate on-chip resistor
ladder and designed in 90-nm CMOS technology, the ADC
achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes
a 233-MHz input with 53-dB SNDR while consuming 55 mW
from a 1.2-V supply. |
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发表于 2010-2-20 18:33:16
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