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As digital systems become more complex, it becomes increasingly important to verify the
functionality of a design before implementing it in a system. Hardware Descriptions
Languages (HDL’s) have become extremely popular because the same language can be
used by engineers for both designing and testing CPLD’s and FPGA’s. The two most
common HDL’s are Verilog and VHDL. This document focuses on using Verilog HDL
to test digital systems, by giving the designer a handful of simulation techniques that can
be used on the majority of digital applications. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2006-8-24 00:10:17
